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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SM5841HS датащи(PDF) 13 Page - Nippon Precision Circuits Inc |
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SM5841HS датащи(HTML) 13 Page - Nippon Precision Circuits Inc |
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13 / 20 page  SM5841H NIPPON PRECISION CIRCUITS—13 Audio Data Input (DIN, BCKI, LRCI) The input data is in 16/18-bit serial, 2s complement, MSB first format. Serial input data on DIN is clocked into an SIPO (serial in, parallel out) register on the rising edge of the BCKI bit clock, and then converted to parallel data. SIPO output data is transferred into the left and right-channel input registers on the falling edge and rising edge, respectively, of the LRCI clock. The internal arithmetic operation and output circuit timing is independent of the input timing. Accord- ingly, phase differences between LRCI, BCKI and CKI do not affect device operation, and any jitter in the data input clock does not cause jitter in the output clock. Note that the device should be reset if either or both of the LRCI and CKI clocks stop. If the device is not reset, even though the clocks are low frequency, incorrect circuit operation may occur, generating unwanted output noise. Figure 3. Audio data input timing DIN LRCI BCKI MSB LSB 1/fs Lch 16 / 18bit 16 / 18bit MSB LSB Rch |
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