CS5307 datasheet(18/24 Pages) ONSEMI

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CS5307

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12 V

TBD

NCi × Ci

ESRCi/NCi

ESRCo/NCo

14 u(t)

NCo × Co

Vi(t = 0) = 12 V

SWNODE

Vo(t = 0) = 1.5 V

VCi

ILo

VOUT

ILi

MAX dI/dt occurs in

first few PWM cycles.

Figure 22. Calculating the Input Inductance

−

4. Input Inductor Selection

The use of an inductor between the input capacitors and

the power source will accomplish two objectives. First, it

will isolate the voltage source and the system from the noise

generated in the switching supply. Second, it will limit the

inrush current into the input capacitors at power up. Large

inrush currents reduce the expected life of the input

capacitors. The inductor’s limiting effect on the input

current slew rate becomes increasingly beneficial during

load transients.

The worst case input current slew rate will occur during

the first few PWM cycles immediately after a step−load

change is applied as shown in Figure 22. When the load is

applied, the output voltage is pulled down very quickly.

Current through the output inductors will not change

instantaneously, so the initial transient load current must be

conducted by the output capacitors. The output voltage will

step downward depending on the magnitude of the output

current (IO,MAX), the per capacitor ESR of the output

capacitors (ESROUT) and the number of the output

capacitors (NOUT) as shown in Figure 22. Assuming the load

current is shared equally between the four phases, the output

voltage at full transient load will be:

VOUT,FULL−LOAD +

(14)

VOUT,NO−LOAD * (IO,MAX 4) @ ESROUT NOUT

When the control MOSFET (Q1 in Figure 22) turns ON,

the input voltage will be applied to the opposite terminal of

the output inductor (the SWNODE). At that instant, the

voltage across the output inductor can be calculated as:

DVLo + VIN * VOUT,FULL−LOAD

(15)

+ VIN * VOUT,NO−LOAD

) (IO,MAX 4) @ ESROUT NOUT

The differential voltage across the output inductor will

cause its current to increase linearly with time. The slew rate

of this current can be calculated from:

dILo dt + DVLo Lo

(16)

Current changes slowly in the input inductor so the input

capacitors must initially deliver the vast majority of the

input current. The amount of voltage drop across the input

capacitors (ΔVCi) is determined by the number of input

capacitors (NIN), their per capacitor ESR (ESRIN) and the

current in the output inductor according to:

DVCi + ESRIN NIN @ dILo dt @ tON

+ ESRIN NIN @ dILo dt @ D fSW

(17)

Before the load is applied, the voltage across the input

inductor (VLi) is very small and the input capacitors charge

to the input voltage VIN. After the load is applied, the voltage

drop across the input capacitors, ΔVCi, appears across the

input inductor as well. Knowing this, the minimum value of

the input inductor can be calculated from:

LiMIN + VLi dIIN dtMAX

+ DVCi dIIN dtMAX

(18)

dIIN/dtMAX is the maximum allowable input current slew

rate.

The input inductance value calculated from Equation 18

is relatively conservative. It assumes the supply voltage is

very “stiff” and does not account for any parasitic elements

that will limit dI/dt such as stray inductance. Also, the ESR

values of the capacitors specified by the manufacturer’s data

sheets are worst case high limits. In reality, input voltage

“sag,” lower capacitor ESRs and stray inductance will help

reduce the slew rate of the input current.

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