CS5132 datasheet(11/20 Pages) ONSEMI

11 / 20 page

Step 1: Define Specification

Input Voltage from “silver box” power supply

• 5V ±5% for conversion to output voltage

• 12V ±5% for NFET Gate Voltage and circuit bias

Output Voltages

• 2.0V @ 16A for VCC(CORE)

• 3.3V@ 8A for VI/O

• 5% Overall Voltage accuracy (load, line, temperature,

ripple)

• 2% DC & 5% AC Voltage Accuracy

• < 2% Output Ripple Voltage

• 15A Load Step @ 20A /µs - VCC(CORE)

• 7A Load Step @ 5A/µs - VI/O

Thermal Management

• 0 to 50° C ambient temperature range

• Component junction temperatures within manufactur-

er’s specified ratings at full load & TA(MAX)

Components

• Low cost is top priority.

• Surface mount when possible

• Small footprint important

• Component Ratings determined at 80% of Maximum

Load

Step 2: Determine Output Capacitors

These components must be selected and placed carefully to

yield optimal results. Capacitors should be chosen to pro-

vide acceptable ripple on the regulator output voltage. Key

specifications for input capacitors are their ripple rating,

while ESR is important for output capacitors. For best tran-

sient response, a combination of low value/high frequency

and bulk capacitors placed close to the load will be

required.

Step 2a: For the 2V Output (VCC(CORE))

The load transients have slew rates of up to 20A /µs, while

the voltage drop during a transient must be kept to less

than 100mV. The output capacitors must hold the output

voltage within these limits since the inductor current can

not change with the required slew rate. The output capaci-

tors must therefore have a very low ESL and ESR.

The voltage transient during the load step is

∆V

OUT = ∆IOUT ×

( +ESR+ )

where tTR = output voltage transient response time.

The total change in output voltage is divided as follows:

ESR - 80mV

ESL - 10mV

Output Capacitor Discharge During Transient - 10mV

Maximum allowable ESR is:

ESR =

= 5.3m

Ω.

The ESR for a 1200µF/10V Sanyo capacitor type GX is

44m

Ω per capacitor.

Number of Capacitors =

≅ 8.

Total ESR =

= 5.5m

Ω.

Output voltage deviation due to ESR:

∆V = 15A × 5.5mΩ = 82mV.

The ESL is calculated from

ESL =

= 0.5nH.

It is estimated that a 10

× 12 mm Aluminum Electrolytic

capacitor has approximately 4nH of package inductance. In

this case we have eight (8) capacitors in parallel for a total

capacitor ESL:

ESL =

= 0.5nH.

Output voltage deviation due to ESL:

∆V =

= 10mV.

The change in capacitor voltage during the transient is:

∆V

C =,

where tTR is the output voltage transient response time. We

choose tTR = 6µs:

∆V

C =

= 9mV.

Total change in output voltage as a result of an increase in

load current of a 15A step with a 20A/µs slew rate is:

∆V

OUT = ( 82mV + 10mV + 9mV ) = 101mV.

Step 2b: For the 3.3V Output (VI/O)

The VI/O load transients have slew rates of 5A/µs, while

the voltage drop during a transient must be kept to less

15A

× 6µs

× 1200µF

∆I × t

COUT

0.5nH

× 20A

1µs

ESL

× ∆I

∆t

4nΗ

0.01V

× 1 × 10−6

∆V × ∆t

∆I

20A

µs

∆I

∆t

5.3

0.08V

15A

tTR

COUT

ESL

∆t

CS5132-based Dual Output

Buck Regulator Design Example

Application Information: continued

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