SN74LS161A, SN74LS163A

http://onsemi.com

5

Symbol

Parameter

Limits

Unit

Test Conditions

Min

Typ

Max

Maximum Clock Frequency

25

32

MHz

Propagation Delay

Clock to TC

20

18

35

35

ns

Propagation Delay

Clock to Q

13

18

24

27

ns

Propagation Delay

CET to TC

9.0

9.0

14

14

ns

MR or SR to Q

20

28

ns

Symbol

Parameter

Limits

Unit

Test Conditions

Min

Typ

Max

Clock Pulse Width Low

25

ns

MR or SR Pulse Width

20

ns

Setup Time, other*

20

ns

Setup Time PE or SR

25

ns

Hold Time, data

3

ns

Hold Time, other

0

ns

Recovery Time MR to CP

15

ns

*CEP, CET, or DATA

DEFINITION OF TERMS

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and

transfer HIGH Data to the Q outputs.

AC WAVEFORMS

Figure 1. Clock to Output Delays, Count

Frequency, and Clock Pulse Width

Figure 2. Master Reset to Output Delay, Master Reset

Pulse Width, and Master Reset Recovery Time

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

CP

Q

Other conditions:

PE = MR (SR) = H

CEP = CET = H

Other conditions:

PE = L

MR

CP