CS5304 datasheet(16/19 Pages) ONSEMI

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CS5304

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works against 10 k

W (R10) to limit the window of fast

slewing to 300 mV − enough to allow for fast transients, but

not enough to interfere with soft−start. This window will be

noticeable as a step in the COMP pin voltage at startup. The

size of this step must be kept smaller than the Channel

Startup Offset (nominally 0.4 V) for proper soft−start

operation. If adaptive positioning is used the R9 and R8 form

a divider with the VDRP end held at the DAC voltage during

startup, which effectively makes the Channel Startup Offset

larger.

C12 is included for error amp stability. A capacitive load

is required on the error amp output. Use of values less than

1.0 nF may result in error amp oscillation of several MHz.

C11 and the parallel resistance of the VFB resistor (R9)

and the VDRP resistor (R8) are used to roll off the error amp

gain. The gain is rolled off at high enough frequency to give

a quick transient response, but low enough to cross zero dB

well below the switching frequency to minimize ripple and

noise on the COMP pin.

Figure 15. External UVLO Circuit

50 k

100 k

+12 V

+5.0 V

COMP

100 k

Layout Guidelines

With the fast rise, high output currents of microprocessor

applications, parasitic inductance and resistance should be

considered when laying out the power, filter and feedback

signal sections of the board. Typically, a multi−layer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to reroute the currents away from the

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

Voltage feedback should be taken from a point of the

output or the output filter that doesn’t favor any one phase.

If the feedback connection is closer to one inductor than the

others the ripple associated with that phase may appear

larger than the ripple associated with the other phases and

poor current sharing can result.

The current sense signal is typically tens of milli−volts.

Noise pick−up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as switch nodes and gate drive signals. The paths

should be matched as well as possible. It is especially

important that all current sense signals be picked off at

similar points for accurate current sharing. If the current

signal is taken from a place other than directly at the inductor

any additional resistance between the pick−off point and the

inductor appears as part of the inherent inductor resistance

and should be considered in design calculations. Capacitors

for the current feedback networks should be placed as close

to the current sense pins as practical.

DESIGN PROCEDURE

Current Sensing, Power Stage and Output Filter

Components

1. Choose the output filter components to meet peak

transient requirements. The formula below can be

used to provide an approximate starting point for

capacitor choice, but will be inadequate to calculate

actual values.

DVPEAK + (DI DT)

ESL ) DI

ESR

Ideally the output filter should be simulated with

models including ESR, ESL, circuit board parasitics

and delays due to switching frequency and converter

response.

Typically

both

bulk

capacitance

(electrolytic, Oscon, etc.,) and low impedance

capacitance (ceramic chip) will be required. The bulk

capacitance provides “hold up” during the converter

response. The low impedance capacitance reduces

steady state ripple and bypasses the bulk capacitance

during slewing of output current.

2. For inductive current sensing (only) choose the

current sense network RC to provide a 25 mV

minimum ramp during steady state operation.

R + (VIN * VOUT)

VOUT VIN

25 mV

Then choose the inductor value and inherent

resistance to satisfy L/RL = R × C.

For ideal current sense compensation the ratio of L and

RL is fixed, so the values of L and RL will be a

compromise typically with the maximum value RL

limited by conduction losses or inductor temperature

rise and the minimum value of L limited by ripple

current.

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