In 1-

2.5V

VIN

¨

©

§

-1

2.5

Ps + 0.25 Ps

In 1-

2.5V

48V

¨

©

§

-1

=

= 51.4

Ps

LM5035A

SNVS537F – JANUARY 2008 – REVISED APRIL 2013

www.ti.com

Soft-Stop

If the UVLO pin voltage falls below the 1.25V standby threshold but above the 0.4V shutdown threshold, the 110

µA SS pin source current is disabled and a 110 µA sink current discharges the soft-start capacitor. As SS voltage

falls and clamps the PWM comparator input, the PWM duty cycle will gradually fall to zero. The soft-stop feature

produces a gradual reduction of the power converter output voltage. This soft-stop method of turning off the

converter reduces energy in the output capacitor before control of the main and synchronous rectification

MOSFETs is disabled. The PWM pulses may cease before the SS voltage reduces the duty cycle if the VCC or

REF voltage drops below the respective under-voltage thresholds during the soft-stop process.

PWM Comparator

The pulse width modulation (PWM) comparator compares the voltage ramp signal at the RAMP pin to the loop

error signal. This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The

loop error signal is received from the external feedback and isolation circuit is in the form of a control current into

the COMP pin. The COMP pin current is internally mirrored by a matched pair of NPN transistors which sink

current through a 5 k

Ω resistor connected to the 5V reference. The resulting control voltage passes through a 1V

level shift before being applied to the PWM comparator.

An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The

bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is

thereby greatly reduced. Higher loop bandwidths can be realized since the bandwidth-limiting pole associated

with the opto-coupler is now at a much higher frequency. The PWM comparator polarity is configured such that

with no current into the COMP pin, the controller produces the maximum duty cycle at the main gate driver

outputs, HO and LO.

Feed-Forward Ramp and Volt • Second Clamp

the PWM ramp signal. The slope of the signal at RAMP will vary in proportion to the input line voltage. This

varying slope provides line feed-forward information necessary to improve line transient response with voltage

mode control. The RAMP signal is compared to the error signal by the pulse width modulator comparator to

with the input voltage (VIN) to stabilize the Volt • Second product of the transformer primary signal. The power

path gain of conventional voltage-mode pulse width modulators (oscillator generated ramp) varies directly with

input voltage. The use of a line generated ramp (input voltage feed-forward) nearly eliminates this gain variation.

As a result, the feedback loop is only required to make very small corrections for large changes in input voltage.

In addition to the PWM comparator, a Volt • Second Clamp comparator also monitors the RAMP pin. If the ramp

ramp capacitor is discharged by an internal 32

Ω discharge MOSFET controlled by the V•S Clamp comparator. If

the RAMP signal does not exceed 2.5V before the end of the clock period, then the internal clock will enable the

duration. The on-time set by the Volt • Second Clamp varies inversely to the line voltage because the RAMP

(2.5V). An example will illustrate the use of the Volt • Second Clamp comparator to achieve a 50% duty cycle

limit at 200kHz with a 48V line input. A 50% duty cycle at a 200kHz requires a 2.5µs on-time. To achieve this

maximum on-time clamp level:

(1)

paired with an 110 k

Ω to approximate the desired 51.4µs time constant. If load transient response is slowed by

16

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