1

2

3

4

BST

VCC

COMP

LO

PGND

CFB

HO

PVIN

5

10

FB

VIN

6

9

RT

EN

7

8

AGND

SS

11

12

13

14

EP

LM5015

SNVS538C – NOVEMBER 2007 – REVISED APRIL 2013

www.ti.com

Connection Diagram

HTSSOP-14 EP Package

Top View

PIN DESCRIPTIONS

Pin

Name

Description

Application Information

1

AGND

Analog ground

Internal reference for the regulator control functions. The AGND pin and the

PGND pin should be connected directly to minimize switching noise and prevent

erratic operation.

2

RT

Oscillator frequency programming

The internal oscillator is set with a resistor between this pin and the AGND pin.

and optional synchronization input

The recommended switching frequency range is 25KHz to 750 kHz. The RT pin

can accept synchronization pulses from an external clock. A 100 pF capacitor is

recommended for coupling the synchronizing clock to the RT pin.

3

FB

Feedback input of the internal error

This pin is connected to the inverting input of the internal error amplifier. The

amplifier, for non-isolated

1.26V reference is internally connected to the non-inverting input of the error

applications

amplifier. In isolated application using an external error amplifier, this pin should

be connected to the AGND pin.

4

COMP

Control input for the PWM

Internally connected to the open drain output of the internal error amplifier.

comparator

COMP pull-up is provided by an internal 5 k

Ω resistor which may be used to

bias an opto-coupler transistor in isolated applications.

5

CFB

Current feedback pin

Feedback in put for high bandwidth isolated applications. An NPN current mirror

couples the external opto-coupler current to the PWM comparator while

maintaining a relatively constant opto-coupler voltage.

6

PGND

Power ground

Internally connected to the current sense resistor in the source of the low side

MOSFET switch.

7

LO

Low side switch drain

The drain terminal of the internal low side power MOSFET.

8

PVIN

Input supply pin for high side switch

Internally connected to the drain of the high side power MOSFET.

9

HO

High side switch source

The source terminal of the high side power MOSFET.

10

BST

High side bootstrap bias

An external capacitor is required between the BST and the HO pins. A minimum

capacitor value of 0.022 µF is recommended. The capacitor is charged from

VCC via an internal diode during the power MOSFET off-time.

11

VCC

Bias regulator output, or input for

VCC tracks VIN up to 6.9V. At higher VIN voltages, VCC is regulated to 6.9

external bias supply

Volts. A 0.47µF or greater ceramic decoupling capacitor is required on the VCC

pin. An external bias voltage between 7V and 14V applied to the VCC pin will

disable the internal VCC regulator, reduce internal power dissipation, and

improve the converter efficiency.

12

VIN

Analog input voltage pin

Power supply Input for the switching regulator control blocks.

13

EN

Enable / Under-Voltage Lock-Out /

An external voltage divider can be used to set the input under-voltage lockout

Shutdown input

threshold. If the EN pin is left unconnected, a 6 µA pull-up current source pulls

the EN pin high to enable the regulator.

14

SS

Soft-start

An internal 11 µA current source charges an external capacitor connected to the

SS pin to soft-start the switching regulator by gradually raising the COMP pin

voltage.

NA

EP

Exposed Pad

Exposed metal pad on the underside of the package. It is recommended to

connect this pad to the PGND and AGND pins, and also to the PC board

ground plane in order to improve heat dissipation.

2

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