CS5111 datasheet(9/16 Pages) ONSEMI

9 / 16 page

CS5111

http://onsemi.com

APPLICATION NOTES

DESIGN PROCEDURE FOR BOOST TOPOLOGY

This section outlines a procedure for designing a boost

switching power supply operating in the discontinuous mode.

Step 1

Determine the output power required by the load.

POUT + IOUTVOUT

(1)

Step 2

Choose COSC based on the target oscillator frequency with

an external resistor value, RBIAS = 64.9 kΩ. (See Figure 5).

Step 3

Next select the output voltage feedback sense resistor

divider as follows (Figure 13).

For VFB1 active, choose a value for R1 and then solve for

REQ where:

REQ +

VOUT

VFB1 *

(2)

For VFB2 active, find:

VFB1 + VOUT

REQ

R1 ) REQ

(3)

and then calculate R2 where:

R2 +

VR2

IR2

VFB1 * VFB2

VFB1 REQ

(4)

Then find R3, where:

R3 + REQ * R2

(5)

Figure 13. Feedback Sense Resistor Divider

Connected Between VOUT and Ground

VOUT

VFB1

VFB2

VR2

REQ

Step 4

Determine the maximum on time at the minimum

oscillator frequency and VIN. For discontinuous operation,

all of the stored energy in the inductor is transferred to the

load prior to the next cycle. Since the current through the

inductor cannot change instantaneously and the inductance

is constant, a volt–second balance exists between the on time

and off time. The voltage across the inductor during the on

cycle is VIN and the voltage across the inductor during the

off cycle is VOUT – VIN. Therefore:

VINtON + (VOUT * VIN)tOFF

(6)

where the maximum on time is:

tON(MAX) [ 1 *

VIN(MIN)

VOUT(MAX)

fSW(MIN)

(7)

Step 5

Calculate

the

maximum

inductance

allowed

for

discontinuous operation:

L(MAX) +

fSW(MIN)VIN2(MIN)tON2(MAX)

2POUT h

(8)

where

η = efficiency.

Usually

η = 0.75 is a good starting point. The IC’s power

dissipation should be calculated after the peak current has

been determined in Step 6. If the efficiency is less than

originally assumed, decrease the efficiency and recalculate

the maximum inductance and peak current.

Step 6

Determine the peak inductor current at the minimum

inductance, minimum VIN and maximum on time to make

sure the inductor current doesn’t exceed 1.4 A.

IPK +

VIN(MIN)tON(MAX)

L(MIN)

(9)

Step 7

Determine the minimum output capacitance and maximum

ESR based on the allowable output voltage ripple.

COUT(MIN) +

IPK

DVRIPPLE

(10)

ESR(MIN) +

DVRIPPLE

IPK

(11)

In practice, it is normally necessary to use a larger

capacitance value to obtain a low ESR. By placing

capacitors in parallel, the equivalent ESR can be reduced.

Step 8

Compensate the feedback loop to guarantee stability

under all operating conditions. To do this, we calculate the

modulator gain and the feedback resistor network

attenuation and set the gain of the error amplifier so that the

overall loop gain is 0 dB at the crossover frequency, fCO. In

addition, the gain slope should be –20 dB/decade at the

crossover frequency.

The low frequency gain of the modulator (i.e. error

amplifier output to output voltage) is:

DVOUT

DVEA

IPK(MAX)

VEA(MAX)

RLOADLf

(12)

where:

IPK(MAX) +

VEA(MAX) GCSA

2.4 V 7

150 m

W +

2.3 A (13)

The VOUT/VEA transfer function has a pole at:

CS5111 датащи(PDF) 9 Page - ON Semiconductor

CS5111 датащи(HTML) 9 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

датащи скачать

ссылки URL