ML6460

15

CLK

HSYNC

(input)

YCrCb

BL

BL

A

B

C

D

E

F

GH

Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0)

Beginning of

Active Line

(0,0)

CB0

Y0

CR0

Y1

CB2

Y2

CR2

Y3

(0,1)

BL

CB0

Y0

CR0

Y1

CB2

Y2

CR2

(1,0)

BL

BL

CB0

Y0

CR0

Y1

CB2

Y2

(1,1)

BL

BL

BL

CB0

Y0

CR0

Y1

CB2

A

B

C

D

E

F

G

H

Bit

Value (SEL_HSYNC1, SEL_HSYNC0)

Figure 7. Pixel Synchronization. For External Mode, Active Edge at Beginning of Active Video.

(HRESET_MODE = 1, SENSE_HSYNC = 0, BL = Blanked Pixel)

(ANALOG_HRESET = ANALOG_HBLANK = 0 OR ANALOG_HRESET = ANALOG_HBLANK = 1)

Figure 7a. Pixel Synchronization. For External Mode, Active Edge at Beginning of Active Video.

(HRESET_MODE = 1, SENSE_HSYNC = 1, BL = Blanked Pixel)

(ANALOG_HRESET = ANALOG_HBLANK = 0 OR ANALOG_HRESET = ANALOG_HBLANK = 1)

CLK

HSYNC

(input)

YCrCb

BL

BL

A

B

C

D

E

F

GH

Selectable Delay Synchronization (SEL_HSYNC1, SEL_HSYNC0)

Beginning of

Active Line

(0,0)

CB0

Y0

CR0

Y1

CB2

Y2

CR2

Y3

(0,1)

BL

CB0

Y0

CR0

Y1

CB2

Y2

CR2

(1,0)

BL

BL

CB0

Y0

CR0

Y1

CB2

Y2

(1,1)

BL

BL

BL

CB0

Y0

CR0

Y1

CB2

A

B

C

D

E

F

G

H

Bit

Value (SEL_HSYNC1, SEL_HSYNC0)