8

ML4821

Micro Linear

ENABLE

–

+

–

+

15

16

INTERNAL

BIAS

4.4V

LOGIC

POWER

9V

500

0

0

100

300

400

500

SINE INPUT CURRENT (µA)

200

100

200

300

400

1.0

1.5

2.5

3.5

4.5

5.5

Figure 8. Under-Voltage Lockout Block Diagram.

Figure 7. Gain Modulator Linearity.

0

–4.0

–8.0

–12

–16

–20

–24

0

20

40

60

80

100

120

40

10

0

010

20

30

20

30

Figure 9. Total Supply Current vs. Supply Voltage.

Figure 10. Reference Load Regulation.

UNDER VOLTAGE LOCKOUT,

OVP AND CURRENT LIMIT

On power-up the ML4821 remains in the UVLO

condition; output low and quiescent current low. The IC

drops below 9V, the UVLO condition is imposed. During

usable as a “flag” for starting up a down-stream PWM

converter.

OVP, SHUTDOWN, AND IC BIAS

output of the ML4821 is inhibited. The OVP input also

functions as a “sleep” input, putting the IC into the low

quiescent UVLO state when the OVP pin is pulled below

0.7V.