ML4658

12

The transmitter incorporates a pre-equalization circuit for

driving the twisted pair line. Pre-equalization

compensates for the amplitude and phase distortion

introduced by the twisted pair cable. The twisted pair line

will attenuate the 10MHz signal more than the 5MHz

signal. Therefore pre-equalization insures that both the 5

and 10MHz components will be roughly the same

amplitude at the far end receiver.

The pre-equalization circuit reduces the current output

when a 5MHz bit is being transmitted. After 50ns of a

5MHz bit, the current level is reduced to approximately

2/3 of its peak for the remaining 50ns. Figure 11 illustrates

the pre-equalization.

An on-chip one-shot determines the pulse width of the

pre-equalized transmit signal. This requires an external

capacitor connected to pins TxCAP0 and TxCAP1. The

proper value for this one-shot is 330pF. Pre-equalization

can be disabled by shorting TxCAP0 and TxCAP1 together.

The transmitter enters the idle state when it detects start

of idle on Tx+ and Tx– input pins. The transmitter

maintains a minimum differential output voltage of at

least 450mV for 250ns after the last low to high transition.

The driver differential output voltage will then be within

50mV of 0V within 45 bit times.

RECEPTION

The twisted pair receive data is transformer coupled and

low pass filtered before it is fed into the input pins RxTP±.

The input is differential with the common mode voltage

set by the chip’s Bias pin. At the start of packet reception

from the twisted pair link, no more than 5 bits are received

from the twisted pair cable and not transmitted onto the DI

circuit. The first bit sent on the DI circuit may contain phase

violations or invalid data, but all subsequent bits are valid.

The receive squelch will reject the following signals on

the RxTP+ and RxTP– inputs:

1. All signals that produce a peak magnitude less than

300mV.

2. All continuous sinusoidal signals of amplitude less than

3. All single sinusoidal cycles of amplitude less than

between 2MHz and 15MHz. For a period of 4 BT

before and after this single cycle, the signal will

conform to (1) above.

4. All sinusoidal cycles gated by a 100ns pulse gate of

the sinusoidal frequency is between 2MHz and

30MHz. The off time of the pulse gate on the sinusoidal

signal shall be at least 400ns.

The first three receive squelch criteria are required to

conform to the 10BASE-T standard. The fourth receive

squelch criteria exceeds the 10BASE-T requirements and

enhances the performance of the receiver. The fourth

squelch criteria prevents a false unsquelch caused by

cross talk or noise typically found coupling from the

phone lines onto the receive twisted pair.

When the receive squelch is on during idle, the input

voltage must exceed approximately ±450mV peak

several times before unsquelch occurs. If the transmitter is

inactive, the receiver has up to 5 bit times to unsquelch

and output the receive data on the Rx+, Rx– pair. If the

transmitter is active, the receive squelch extends the time

it takes to determine whether to unsquelch. If the receiver

unsquelches while the transmitter is active, a collision

will result. Therefore the receive squelch uses the

additional time to insure that a collision will not be

reported as a result of a false receive squelch.

After the receiver is unsquelched, the detection threshold

is lowered to 275mV. Upon passing the receive squelch

requirements the receive data propagates into the

multiplexer and eventually passes to the Rx+ and Rx–

outputs of the AU interface. The addition of jitter through

the receive section is no more than ±1.5ns.

While in the unsquelch state, the receive squelch circuit

looks for the start of idle signal at the end of the packet.

When start of idle is detected, receive squelch is turned

on again. The proper start of idle occurs when the input

signal remains above 300mV for 160ns. Nevertheless, if

no transitions occur for 160ns, receive squelch is still

turned on.

COLLISION

Whenever the receiver and the transmitter are active at

the same time the chip will activate the collision output.

The collision output is a differential square wave

matching the AUI specifications and capable of driving a

78

Ωload. The frequency of the square wave is 10MHz

±15% with a 60/40 to 40/60 duty cycle. The collision

oscillation turns on no more than 9 bit times after the

collision condition begins, and turns off no more than 9

bit times after the collision condition is removed. The

collision oscillator also is activated during SQE Test and

Jabber.

LOOPBACK

The loopback function emulates a coax Ethernet

transceiver where the transmit data sent by the DTE is

looped back over the AUI receive pair. Many LAN

controllers report the status of the carrier sense for each

packet transmitted. The software can use this loopback

information to determine whether a MAU is connected to

the DTE by checking the status of carrier sense after each

packet transmission.