ML2252CCP datasheet(5/13 Pages) MICRO-LINEAR

5 / 13 page

ML2252, ML2259

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC and Dynamic Performance Characteristics (Note 5)

tACQ

Sample and Hold Acquisition

1/2

1/fCLK

fCLK

Clock Frequency

1460

kHz

Conversion Time

8.5

8.5 + 250ns

1/fCLK

SNR

Signal to Noise Ratio

VIN = 51kHz, 5V sine.

fCLK = 1.46MHz

(fSAMPLING > 150kHz). Noise is sum

of all nonfundamental components

up to 1/2 of fSAMPLING

THD

Total Harmonic Distortion

VIN = 51kHz, 5V sine.

–60

fCLK = 1.46MHz

(fSAMPLING > 150kHz).

THD is sum 2, 3, 4, 5 harmonics

relative to fundamental

IMD

Intermodulation Distortion

VIN = fA + fB. fA = 49kHz, 2.5V sine.

–60

fB = 47.8kHz, 2.5V sine,

fCLK = 1.46MHz

(fSAMPLING > 150kHz). IMD is (fA + fB),

(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),

(fA – 2fB) relative to fundamental

Frequency Response

VIN = 0 to 50kHz. 5V sine relative

0.1

to 1kHz

tDC

Clock Duty Cycle

(Note 6)

tEOC

End of Conversion Delay

1/2

1/2 + 250ns

1/fCLK

tWS

Start Pulse Width

tSS

Start Pulse Setup Time

Synchronous only, (Note 7)

tWALE

Address Latch Enable

Pulse Width

Address Setup

Address Hold

tH1, H0

Output Enable for DB0–DB7

Figure 1, CL = 50pF

100

Figure 1, CL = 10pF

t1H, 0H

Output Disable for DB0–DB7

Figure 1, CL = 50pF

100

Figure 1, CL = 10pF

CIN

Capacitance of Logic Input

COUT

Capacitance of Logic Outputs

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.

Note 3: For –VREF • VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages

one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can

cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either

diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an

absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading.

Note 4: Leakage current is measured with the clock not switching.

Note 5: CL = 50pF, timing measured at 50% point.

Note 6: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,

the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs.

Note 7: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,

start conversion will have an uncertainty of one clock pulse.

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