LM5019 datasheet(21/30 Pages) TI

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VIN(UVLO, rising) = 1.225V x

RUV2

+ 1

)

(

RUV1

VIN (HYS) = IHYS x RUV2

OUT(MAX)

´ ´ D

LM5019

www.ti.com

SNVS788F – JANUARY 2012 – REVISED DECEMBER 2014

8.2.2.2.11

Input Capacitor

The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and a

larger bulk capacitor. The total input capacitance should be large enough to limit the input voltage ripple to a

desired amplitude. For input ripple voltage

ΔVIN, CIN can be calculated using Equation 26.

(26)

Choosing a

ΔVIN of 0.5 V gives a minimum CIN of 0.067 μF. A standard value of 0.1 μF is selected for for CBYP in

this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the

power source to the converter. A standard value of 1

μF is selected for for CIN in this design. The voltage ratings

of the two input capacitors should be greater than the maximum input voltage under all conditions.

8.2.2.2.12

UVLO Resistors

UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 27

and Equation 28.

(27)

(28)

Where IHYS = 20 μA, typical.

For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 27 and Equation 28 require RUV1 of

8.25 k

Ω and RUV2 of 127 kΩ and these values are selected for this design example.

8.2.2.2.13

VCC Diode

Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more

than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in

reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to a

voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias

current.

8.2.2.3 Application Curves

VIN = 48 V

IOUT1 = 0 mA

IOUT2 = 100 mA

Figure 22. Steady State Waveform

Figure 21. Efficiency at 750 kHz, VOUT1 = 10 V

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