TC850

DS21479C-page 18

© 2006 Microchip Technology Inc.

FIGURE 8-4:

Conversion Timing, Demand Mode

FIGURE 8-5:

Bus Output Timing, Demand Mode

WR Pulses are Ignored

836 Clock Cycles

1100 Clock Cycles

Internal Clock

BUSY

DB0-DB7

CS . CE

Next Convert

Command will be

Recognized

Previous Conversion

Data Valid

Data Meaningless

New Conversion Data Valid

Next Conversion

can Begin

319 Clock

Cycles

125 Clock

Cycles

. . . .

. . . . . . . .

WR

DB0-DB6

DB7

OVR/POL

L/H

TCE

TDHC

TDHR

TRE

CS . CE

HI-Z

*

Data Bits 8 to 14

High-Impedance

High-Impedance

Don't Care

Don't Care

Data Bits 0 tp 6

HI-Z

"1"= Input

Overrange

"1"= Positive

Polarity

Data Bit 7

tOP

TLH

RD

NOTE: CONT/DEMAND = LOW

*RD (as well as CS and CE) can go HIGH after each byte is read (i.e., in a mP bus interface)

or remain LOW during the entire DATA-READ sequence (i.e., mP I/O port interface).