TC835 datasheet(7/24 Pages) MICROCHIP

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DS21478B-page 7

TC835

3.0

DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

3.1

Dual Slope Conversion Principles

The TC835 is a dual slope, integrating analog to digital

converter. An understanding of the dual slope conver-

sion technique will aid in following the detailed TC835

operational theory.

The conventional dual slope converter measurement

cycle has two distinct phases:

Input signal integration

Reference voltage integration (de-integration)

The input signal being converted is integrated for a fixed

time period, with time being measured by counting clock

pulses. An opposite polarity constant reference voltage

is then integrated until the integrator output voltage

returns to zero. The reference integration time is directly

proportional to the input signal.

simple

dual

slope

converter,

complete

conversion requires the integrator output to "ramp-up"

and "ramp-down."

A simple mathematical equation relates the input sig-

nal, reference voltage and integration time:

EQUATION 3-1:

For a constant VIN:

EQUATION 3-2:

The dual slope converter accuracy is unrelated to the

integrating resistor and capacitor values, as long as

they are stable during a measurement cycle. An

inherent benefit is noise immunity. Noise spikes are

integrated, or averaged, to zero during the integration

periods. Integrating ADCs are immune to the large

conversion errors that plague successive approxima-

tion converters in high noise environments (see

Figure 3-1).

FIGURE 3-1:

BASIC DUAL SLOPE

CONVERTER

3.2

TC835

Operational Theory

The TC835 incorporates a system zero phase and

integrator output voltage zero phase to the normal two

phase dual slope measurement cycle. Reduced sys-

tem errors, fewer calibration steps and a shorter over-

range recovery time result.

The TC835 measurement cycle contains four phases:

System zero

Analog input signal integration

Reference voltage integration

Integrator output zero

Internal analog gate status for each phase is shown in

Table 3-1.

3.2.1

SYSTEM ZERO

During this phase, errors due to buffer, integrator and

comparator offset voltages are compensated for by

charging CAZ (auto zero capacitor) with a compensat-

ing error voltage. With a zero input voltage the

integrator output will remain at zero.

The external input signal is disconnected from the inter-

nal circuitry by opening the two SWI switches. The

internal input points connect to ANALOG COMMON.

The reference capacitor charges to the reference

voltage potential through SWR. A feedback loop,

closed around the integrator and comparator, charges

the CAZ capacitor with a voltage to compensate for

buffer amplifier, integrator and comparator offset

voltages (see Figure 3-2).

RINTCINT∫

TINT

VIN(T)DT =

VREF TDEINT

RINTCINT

where:

VREF

= Reference voltage

TINT

= Signal integration time (fixed)

TDEINT = Reference voltage integration time

(variable).

VIN =

VREF TDEINT

tINT

REF

Voltage

Analog Input

Signal

Display

Switch

Drive

Control

Logic

Clock

Counter

Polarity Control

Phase

Control

VIN ≈ VREF

Variable

Reference

Integrate

Time

Fixed

Signal

Integrate

Time

Integrator

Comparator

VIN ≈ 1/2 VREF

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