LM5116WGSLASHNOPB datasheet(21/34 Pages) TI

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VOUT

1.215V

RFB2

RFB1

- 1

tSS x 10 PA

CSS =

1.215V

'VHB

CHB t

RIN + ESR

ZIN

POUT

VIN

ZIN = -

LM5116WG

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SNVS599D – OCTOBER 2008 – REVISED FEBRUARY 2013

The converter exhibits a negative input impedance which is lowest at the minimum input voltage:

(19)

The damping factor for the input filter is given by:

(20)

where RIN is the input wiring resistance and ESR is the series resistance of the input capacitors. The term ZS/ZIN

will always be negative due to ZIN.

When

δ = 1, the input filter is critically damped. This may be difficult to achieve with practical component values.

With

δ < 0.2, the input filter will exhibit significant ringing. If δ is zero or negative, there is not enough resistance

in the circuit and the input filter will sustain an oscillation. When operating near the minimum input voltage, an

aluminum electrolytic capacitor across CIN may be needed to damp the input for a typical bench test setup. Any

parallel capacitor should be evaluated for its RMS current rating. The current will split between the ceramic and

aluminum capacitors based on the relative impedance at the switching frequency.

VCC CAPACITOR

The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and

bootstrap diode (D1) as well as provide stability for the VCC regulator. These current peaks can be several

amperes. The recommended value of CVCC should be no smaller than 0.47 µF, and should be a good quality, low

ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused

by trace inductance. A value of 1 µF was selected for this design.

BOOTSTRAP CAPACITOR

The bootstrap capacitor (CHB) between the HB and SW pins supplies the gate current to charge the high-side

MOSFET gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).

These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1

µF, and should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially

damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap

capacitor is calculated as:

(21)

Where Qg is the high-side MOSFET gate charge and ΔVHB is the tolerable voltage droop on CHB, which is

typically less than 5% of VCC. A value of 1 µF was selected for this design.

SOFT-START CAPACITOR

The capacitor at the SS pin (CSS) determines the soft-start time, which is the time for the reference voltage and

the output voltage to reach the final regulated value. The soft-start time tSS should be substantially longer than

the time required to charge COUT to VOUT at the maximum output current. To meet this requirement:

tSS > VOUT x COUT / (ICURRENT LIMIT − IOUT)

(22)

The value of CSS for a given time is determined from:

(23)

For this application, a value of 0.01 µF was chosen for a soft-start time of 1.2 ms.

OUTPUT VOLTAGE DIVIDER

RFB1 and RFB2 set the output voltage level, the ratio of these resistors is calculated from:

(24)

RFB1 is typically 1.21 kΩ for a divider current of 1 mA. The divider current can be reduced to 100 µA with

RFB1=12.1 kΩ. For the 5V output design example used here, RFB1 = 1.21 kΩ and RFB2 = 3.74 kΩ.

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