W94AD6KB datasheet(13/60 Pages) WINBOND

13 / 60 page

W94AD6KB / W94AD2KB

Publication Release Date: Oct. 02, 2014

Revision: A01-005

- 13 -

7.1.2

Initialization Waveform Sequence

VDD

VDDQ

CKE

Command

Address

A10

BA0,BA1

DQ, DQS

200µs

tCK

tRP

tRFC

tMRD

NOP

PRE

ARF

MRS

ACT

CODE

All

Banks

(High-Z)

VDD / VDDQ powered up

Clock stable

Load

Mode Reg.

= Don't Care

BA0 = L

BA1 = H

BA0 = L

BA1 = L

Load

Ext. Mode Reg.

7.2

Mode Register Set Operation

The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This

definition includes the definition of a burst length, a burst type, a CAS latency as shown in the

following figure.

The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and

BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep

Power Down mode, or the device loses power.

Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-

A6 the CAS latency. A logic 0 should be programmed to all the undefined addresses bits to ensure

future compatibility.

The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time tMRD before initiating any subsequent operation. Violating either

of these requirements will result in unspecified operation.

Reserved states should not be used, as unknown operation or incompatibility with future versions may

result.

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