PIC16LC62B-04SLASHP datasheet(44/120 Pages) MICROCHIP

44 / 120 page

PIC16C62B/72A

DS35008B-page 44

Preliminary

8.3.1.3

TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and the CKP will be cleared by

hardware, holding SCL low. Slave devices cause the

master to wait by holding the SCL line low. The transmit

data is loaded into the SSPBUF register, which in turn

loads the SSPSR register. When bit CKP (SSP-

CON<4>) is set, pin RC3/SCK/SCL releases SCL.

When the SCL line goes high, the master may resume

operating the SCL line and receiving data. The master

must monitor the SCL pin prior to asserting another

clock pulse. The slave devices may be holding off the

master by stretching the clock. The eight data bits are

shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time (Figure 8-4).

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register used to determine the status of

the byte. Flag bit SSPIF is set on the falling edge of the

ninth clock pulse.

As a slave-transmitter, the ACK pulse from the master-

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then the

data transfer is complete. When the ACK is latched by

the slave, the slave logic is reset (resets SSPSTAT reg-

ister) and the slave then monitors for another occur-

rence of the START bit. If the SDA line was low (ACK),

the transmit data must be loaded into the SSPBUF reg-

ister, which also loads the SSPSR register. Then pin

RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 8-4:

I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

ACK

Transmitting Data

R/W = 1

Receiving Address

789

123

cleared in software

SSPBUF is written in software

From SSP interrupt

service routine

Set bit after writing to SSPBUF

Data in

sampled

SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written-to

before the CKP bit can be set)

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