PIC876 datasheet(126/218 Pages) MICROCHIP

126 / 218 page

PIC16F87X

DS30292C-page 124

 2001 Microchip Technology Inc.

12.4

Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.2V - 1.7V). To

take advantage of the POR, tie the MCLR pin directly

(or through a resistor) to VDD. This will eliminate

external RC components usually needed to create a

Power-on Reset. A maximum rise time for VDD is spec-

ified. See Electrical Specifications for details.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. Brown-out Reset may be used to meet the

start-up conditions. For additional information, refer to

Application Note, AN007, “Power-up Trouble Shoot-

ing”, (DS00007).

12.5

Power-up Timer (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up only from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in RESET as long as the PWRT is active.

The PWRT’s time delay allows VDD to rise to an accept-

able level. A configuration bit is provided to enable/dis-

able the PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

12.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a delay of

1024 oscillator cycles (from OSC1 input) after the

PWRT delay is over (if PWRT is enabled). This helps to

ensure that the crystal oscillator or resonator has

started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or Wake-up from

SLEEP.

12.7

Brown-out Reset (BOR)

The configuration bit, BODEN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(parameter #35, about 100

µS), the brown-out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in RESET for

TPWRT (parameter #33, about 72mS). If VDD should fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess will restart when VDD rises above VBOR with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

12.8

Time-out Sequence

On power-up, the time-out sequence is as follows: The

PWRT delay starts (if enabled) when a POR Reset

occurs. Then OST starts counting 1024 oscillator

cycles when PWRT ends (LP, XT, HS). When the OST

ends, the device comes out of RESET.

If MCLR is kept low long enough, the time-outs will

expire. Bringing MCLR high will begin execution imme-

diately. This is useful for testing purposes or to synchro-

nize more than one PIC16F87X device operating in

parallel.

Table 12-5 shows the RESET conditions for the STA-

TUS, PCON and PC registers, while Table 12-6 shows

the RESET conditions for all the registers.

12.9

Power Control/Status Register

(PCON)

The Power Control/Status Register, PCON, has up to

two bits depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is

unknown on a Power-on Reset. It must then be set by

the user and checked on subsequent RESETS to see if

bit BOR cleared, indicating a BOR occurred. When the

Brown-out Reset is disabled, the state of the BOR bit is

unpredictable and is, therefore, not valid at any time.

Bit1 is POR (Power-on Reset Status bit). It is cleared on

a Power-on Reset and unaffected otherwise. The user

must set this bit following a Power-on Reset.

TABLE 12-3:

TIME-OUT IN VARIOUS SITUATIONS

Oscillator Configuration

Power-up

Brown-out

Wake-up from

SLEEP

PWRTE = 0

PWRTE = 1

XT, HS, LP

72 ms + 1024TOSC

1024TOSC

72 ms + 1024TOSC

1024TOSC

72 ms

—

72 ms

—

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