PIC18C242-ISLASHP datasheet(21/296 Pages) MICROCHIP

21 / 296 page

PIC18CXX2

Preliminary

DS39026B-page 21

2.7

Effects of Sleep Mode on the On-chip

Oscillator

When the device executes a SLEEP instruction, the on-

chip clocks and oscillator are turned off and the device

is held at the beginning of an instruction cycle (Q1

state). With the oscillator off, the OSC1 and OSC2 sig-

nals will stop oscillating. Since all the transistor switch-

ing currents have been removed, sleep mode achieves

the lowest current consumption of the device (only

leakage currents). Enabling any on-chip feature that

will operate during sleep will increase the current con-

sumed during sleep. The user can wake from SLEEP

through external reset, Watchdog Timer Reset or

through an interrupt.

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

2.8

Power-up Delays

Power up delays are controlled by two timers, so that no

external reset circuitry is required for most applications.

The delays ensure that the device is kept in RESET

until the device power supply and clock are stable. For

additional information on RESET operation, see the

“Reset” section.

The first timer is the Power-up Timer (PWRT), which

optionally provides a fixed delay of 72 ms (nominal) on

power-up only (POR and BOR). The second timer is

the Oscillator Start-up Timer OST, intended to keep the

chip in RESET until the crystal oscillator is stable.

With the PLL enabled (HS/PLL oscillator mode), the

time-out sequence following a power-on reset is differ-

ent from other oscillator modes. The time-out sequence

is as follows: First the PWRT time-out is invoked after a

POR time delay has expired. Then the Oscillator Start-

up Timer (OST) is invoked. However, this is still not a

sufficient amount of time to allow the PLL to lock at high

frequencies. The PWRT timer is used to provide an

additional fixed 2ms (nominal) time-out to allow the PLL

ample time to lock to the incoming clock frequency.

OSC Mode

OSC1 Pin

OSC2 Pin

Floating, external resistor should pull

high

At logic low

RCIO

Floating, external resistor should pull

high

Configured as Port A, bit 6

ECIO

Floating

Configured as Port A, bit 6

Floating

At logic low

LP, XT, and HS

Feedback inverter disabled, at quies-

cent voltage level

Feedback inverter disabled, at quies-

cent voltage level

See Table 3-1, in the “Reset” section, for time-outs due to Sleep and MCLR reset.

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