PIC17C752-08SLASHPQ datasheet(44/320 Pages) MICROCHIP

44 / 320 page

PIC17C75X

DS30264A-page 44

Preliminary

TABLE 7-3: SPECIAL FUNCTION REGISTERS

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets (3)

Unbanked

00h

INDF0

Uses contents of FSR0 to address data memory (not a physical register)

---- ----

01h

FSR0

Indirect data memory address pointer 0

xxxx xxxx

uuuu uuuu

02h

PCL

Low order 8-bits of PC

0000 0000

03h(1)

PCLATH

Holding register for upper 8-bits of PC

0000 0000

uuuu uuuu

04h

ALUSTA

FS3

FS2

FS1

FS0

1111 xxxx

1111 uuuu

05h

T0STA

INTEDG

T0SE

T0CS

T0PS3

T0PS2

T0PS1

T0PS0

—

0000 000-

06h(2)

CPUSTA

—

STKAV

GLINTD

POR

BOR

--11 1100

--11 qquu

07h

INTSTA

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

0000 0000

08h

INDF1

Uses contents of FSR1 to address data memory (not a physical register)

---- ----

09h

FSR1

Indirect data memory address pointer 1

xxxx xxxx

uuuu uuuu

0Ah

WREG

Working register

xxxx xxxx

uuuu uuuu

0Bh

TMR0L

TMR0 register; low byte

xxxx xxxx

uuuu uuuu

0Ch

TMR0H

TMR0 register; high byte

xxxx xxxx

uuuu uuuu

0Dh

TBLPTRL

Low byte of program memory table pointer

0000 0000

0Eh

TBLPTRH

High byte of program memory table pointer

0000 0000

0Fh

BSR

Bank select register

0000 0000

Bank 0

10h

PORTA

RBPU

—

RA5/TX1/

CK1

RA4/RX1/

DT1

RA3/SDI/

SDA

RA2/SS/

SCL

RA1/T0CKI

RA0/INT

0-xx xxxx

0-uu uuuu

11h

DDRB

Data direction register for PORTB

1111 1111

12h

PORTB

RB7/

SDO

RB6/

SCK

RB5/

TCLK3

RB4/

TCLK12

RB3/

PWM2

RB2/

PWM1

RB1/

CAP2

RB0/

CAP1

xxxx xxxx

uuuu uuuu

13h

RCSTA1

SPEN

RX9

SREN

CREN

—

FERR

OERR

RX9D

0000 -00x

0000 -00u

14h

RCREG1

Serial port receive register

xxxx xxxx

uuuu uuuu

15h

TXSTA1

CSRC

TX9

TXEN

SYNC

—

TRMT

TX9D

0000 --1x

0000 --1u

16h

TXREG1

Serial Port Transmit Register (for USART1)

xxxx xxxx

uuuu uuuu

17h

SPBRG1

Baud Rate Generator Register (for USART1)

xxxx xxxx

uuuu uuuu

Bank 1

10h

DDRC

Data direction register for PORTC

1111 1111

11h

PORTC

RC7/

AD7

RC6/

AD6

RC5/

AD5

RC4/

AD4

RC3/

AD3

RC2/

AD2

RC1/

AD1

RC0/

AD0

xxxx xxxx

uuuu uuuu

12h

DDRD

Data direction register for PORTD

1111 1111

13h

PORTD

RD7/

AD15

RD6/

AD14

RD5/

AD13

RD4/

AD12

RD3/

AD11

RD2/

AD10

RD1/

AD9

RD0/

AD8

xxxx xxxx

uuuu uuuu

14h

DDRE

Data direction register for PORTE

---- 1111

15h

PORTE

—

RE3/

CAP4

RE2/WR

RE1/OE

RE0/ALE

---- xxxx

---- uuuu

16h

PIR1

RBIF

TMR3IF

TMR2IF

TMR1IF

CA2IF

CA1IF

TX1IF

RC1IF

x000 0010

u000 0010

17h

PIE1

RBIE

TMR3IE

TMR2IE

TMR1IE

CA2IE

CA1IE

TX1IE

RC1IE

0000 0000

Legend:

x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.

Note 1:

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated

from or transferred to the upper byte of the program counter.

The TO and PD status bits in CPUSTA are not affected by a MCLR reset.

Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.

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