PIC18F2220 datasheet(37/388 Pages) MICROCHIP

37 / 388 page

 2003 Microchip Technology Inc.

DS39599C-page 35

PIC18F2220/2320/4220/4320

3.3.3

RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator

block using the INTOSC multiplexer. This mode allows

for controllable power conservation during Idle periods.

This mode is entered by setting the IDLEN bit, setting

SCS1 (SCS0 is ignored) and executing a SLEEP

instruction. The INTOSC multiplexer may be used to

select a higher clock frequency by modifying the IRCF

bits before executing the SLEEP instruction. When the

clock source is switched to the INTOSC multiplexer

(see Figure 3-7), the primary oscillator is shut down

and the OSTS bit is cleared.

If the IRCF bits are set to a non-zero value (thus

enabling the INTOSC output), the IOFS bit becomes

set after the INTOSC output becomes stable, in about

1 ms. Clocks to the peripherals continue while the

INTOSC source stabilizes. If the IRCF bits were previ-

ously at a non-zero value before the SLEEP instruction

was executed and the INTOSC source was already

stable, the IOFS bit will remain set. If the IRCF bits are

all clear, the INTOSC output is not enabled and the

IOFS bit will remain clear; there will be no indication of

the current clock source.

When a wake-up event occurs, the peripherals con-

tinue to be clocked from the INTOSC multiplexer. After

a 10

µs delay following the wake-up event, the CPU

begins executing code, being clocked by the INTOSC

multiplexer. The microcontroller operates in RC_RUN

mode until the primary clock becomes ready. When the

primary clock becomes ready, a clock switch back to

the primary clock occurs (see Figure 3-8). When the

clock switch is complete, the IOFS bit is cleared, the

OSTS bit is set and the primary clock is providing the

system clock. The IDLEN and SCS bits are not affected

by the wake-up. The INTRC source will continue to run

if either the WDT or the Fail-Safe Clock Monitor is

enabled.

FIGURE 3-7:

TIMING TRANSITION TO RC_IDLE MODE

FIGURE 3-8:

TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2

Clock Transition

Q3 Q4

OSC1

Peripheral

Program

PC + 2

INTOSC

PLL Clock

PC + 6

Output

CPU Clock

PC + 4

Clock

Counter

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

Wake-up from Interrupt Event

TOST(1)

TPLL(1)

345

Clock Transition

OSTS bit Set

Multiplexer

PIC18F2220 датащи(PDF) 37 Page - Microchip Technology

PIC18F2220 датащи(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL