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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC18C601 датащи(PDF) 86 Page - Microchip Technology |
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PIC18C601 датащи(HTML) 86 Page - Microchip Technology |
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86 / 320 page  PIC18C601/801 DS39541A-page 86 Advance Information 2001 Microchip Technology Inc. 7.1 Operation Example 7-1 shows the sequence to perform an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 7-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s most significant bit (MSb) is tested and the appropriate subtractions are done. EXAMPLE 7-1: 8 x 8 UNSIGNED MULTIPLY ROUTINE EXAMPLE 7-2: 8 x 8 SIGNED MULTIPLY ROUTINE Example 7-3 shows the sequence to perform a 16 x 16 unsigned multiply. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in 4 registers RES3:RES0. EQUATION 7-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM EXAMPLE 7-3: 16 x 16 UNSIGNED MULTIPLY ROUTINE Example 7-4 shows the sequence to perform a 16 x 16 signed multiply. Equation 7-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the argu- ments, each argument pairs’ most significant bit (MSb) is tested and the appropriate subtractions are done. EQUATION 7-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM MOVFF ARG1, WREG ; MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL MOVFF ARG1, WREG MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH ; - ARG1 MOVFF ARG2, WREG BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH ; PRODH = PRODH ; - ARG2 RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216)+ (ARG1H • ARG2L • 28)+ (ARG1L • ARG2H • 28)+ (ARG1L • ARG2L) MOVFF ARG1L, WREG MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MOVFF PRODH, RES1 ; MOVFF PRODL, RES0 ; ; MOVFF ARG1H, WREG MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL MOVFF PRODH, RES3 ; MOVFF PRODL, RES2 ; ; MOVFF ARG1L, WREG MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1 ; Add cross MOVF PRODH, W ; products ADDWFC RES2 ; CLRF WREG ; ADDWFC RES3 ; ; MOVFF ARG1H, WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVF PRODL, W ; ADDWF RES1 ; Add cross MOVF PRODH, W ; products ADDWFC RES2 ; CLRF WREG ; ADDWFC RES3 ; RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216)+ (ARG1H • ARG2L • 28)+ (ARG1L • ARG2H • 28)+ (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 216)+ (-1 • ARG1H<7> • ARG2H:ARG2L • 216) |
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