PIC17C752 datasheet(96/328 Pages) MICROCHIP

96 / 328 page

PIC17C7XX

DS30289A-page 96

12.1

Timer0 Operation

When the T0CS (T0STA<5>) bit is set, TMR0 incre-

ments on the internal clock. When T0CS is clear, TMR0

increments on the external clock (RA1/T0CKI pin). The

external clock edge can be selected in software. When

the T0SE (T0STA<6>) bit is set, the timer will increment

on the rising edge of the RA1/T0CKI pin. When T0SE

is clear, the timer will increment on the falling edge of

the RA1/T0CKI pin. The prescaler can be programmed

to introduce a prescale of 1:1 to 1:256. The timer incre-

ments from 0000h to FFFFh and rolls over to 0000h.

On overﬂow, the TMR0 Interrupt Flag bit (T0IF) is set.

The TMR0 interrupt can be masked by clearing the cor-

responding TMR0 Interrupt Enable bit (T0IE). The

TMR0 Interrupt Flag bit (T0IF) is automatically cleared

when vectoring to the TMR0 interrupt vector.

12.2

Using Timer0 with External Clock

When an external clock input is used for Timer0, it is

synchronized

with

the

internal

phase

clocks.

Figure 12-3 shows the synchronization of the external

clock. This synchronization is done after the prescaler.

The output of the prescaler (PSOUT) is sampled twice

in every instruction cycle to detect a rising or a falling

edge. The timing requirements for the external clock

are detailed in the electrical speciﬁcation section.

12.2.1

DELAY FROM EXTERNAL CLOCK EDGE

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time TMR0 is actually

incremented. Figure 12-3 shows that this delay is

between 3TOSC and 7TOSC. Thus, for example, mea-

suring the interval between two edges (e.g. period) will

be accurate within

±4TOSC (±121 ns @ 33 MHz).

FIGURE 12-2: TIMER0 MODULE BLOCK DIAGRAM

FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)

RA1/T0CKI

Synchronization

Prescaler

(8 stage

async ripple

counter)

T0SE

(T0STA<6>)

Fosc/4

T0CS

(T0STA<5>)

T0PS3:T0PS0

(T0STA<4:1>)

TMR0H<8> TMR0L<8>

Interrupt on overﬂow

sets T0IF

(INTSTA<5>)

PSOUT

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Prescaler

output

(PSOUT)

Sampled

Prescaler

output

Increment

TMR0

T0 + 1

T0 + 2

(note 3)

(note 2)

Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.

↑ = PSOUT is sampled here.

3: The PSOUT high time is too short and is missed by the sampling circuit.

(note 1)

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