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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC17C752 датащи(PDF) 71 Page - Microchip Technology |
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PIC17C752 датащи(HTML) 71 Page - Microchip Technology |
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71 / 320 page  © 1997 Microchip Technology Inc. Preliminary DS30264A-page 71 PIC17C75X TABLE 10-3: PORTB FUNCTIONS TABLE 10-4: REGISTERS/BITS ASSOCIATED WITH PORTB Name Bit Buffer Type Function RB0/CAP1 bit0 ST Input/Output or the Capture1 input pin. Software programmable weak pull-up and interrupt on change features. RB1/CAP2 bit1 ST Input/Output or the Capture2 input pin. Software programmable weak pull-up and interrupt on change features. RB2/PWM1 bit2 ST Input/Output or the PWM1 output pin. Software programmable weak pull-up and interrupt on change features. RB3/PWM2 bit3 ST Input/Output or the PWM2 output pin. Software programmable weak pull-up and interrupt on change features. RB4/TCLK12 bit4 ST Input/Output or the external clock input to Timer1 and Timer2. Software programmable weak pull-up and interrupt on change features. RB5/TCLK3 bit5 ST Input/Output or the external clock input to Timer3. Software programmable weak pull-up and interrupt on change features. RB6/SCK bit6 ST Input/Output or the master/slave clock for the SPI. Software programmable weak pull-up and interrupt on change features. RB7/SDO bit7 ST Input/Output or data output for the SPI. Software programmable weak pull-up and interrupt on change features. Legend: ST = Schmitt Trigger input. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets (Note1) 12h PORTB RB7/ SDO RB6/ SCK RB5/ TCLK3 RB4/ TCLK12 RB3/ PWM2 RB2/ PWM1 RB1/ CAP2 RB0/ CAP1 xxxx xxxx uuuu uuuu 11h, Bank 0 DDRB Data direction register for PORTB 1111 1111 1111 1111 10h, Bank 0 PORTA RBPU — RA5/ TX1/CK1 RA4/ RX1/DT1 RA3/ SDI/SDA RA2/ SS/SCL RA1/T0CKI RA0/INT 0-xx xxxx 0-uu uuuu 06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11 07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000 16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010 17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000 16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition. Shaded cells are not used by PORTB. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. |
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