s Max. propagation delay of 800ps

s Enable to Output max. of 950ps

s Extended supply voltage option:

s Voltage and temperature compensation for

improved noise immunity

s Internal 75K

s 50% faster than Fairchild 300K

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

FEATURES

DESCRIPTION

The SY100S313 offers four drivers with two OR and two

NOR outputs, designed for use in high-performance ECL

systems. The four drivers are controlled by a common

Enable signal which is buffered to minimize input loading.

If the D inputs are not used, the Enable signal can be used

to drive sixteen 50

Ω lines. All inputs have 75KΩ pulldown

resistors and all outputs are buffered.

BLOCK DIAGRAM

QUAD DRIVER

E

PIN CONFIGURATIONS

18

17

16

15

14

13

1

2

3

4

5

6

7

24

8

23

9

22

10

21

11

20

12

19

Top View

Flatpack

F24-1

SY100S313

Rev.: G

Amendment: /0

Issue Date:

July, 1999

Pin

Function

Data Inputs (n-1...5)

E

Enable Input

Data Outputs

Complementary Data Outputs

PIN NAMES

E

4

3

2

1

28

27

12

13

14

15

16

17

19

11

20

10

21

9

22

8

23

7

24

6

Top View

PLCC

J28-1

26

18

25

5

1