KMB-001LEVALZ datasheet(21/34 Pages) INTERSIL

21 / 34 page

ISLA214P12

FN7982.2

June 27, 2012

The clock divider can also be controlled through the SPI port,

which overrides the CLKDIV pin setting. See “SPI Physical

Interface” on page 25. A delay-locked loop (DLL) generates

internal clock signals for various stages within the charge

pipeline. If the frequency of the input clock changes, the DLL may

take up to 100μs to regain lock at 125MSPS. The lock time is

inversely proportional to the sample rate.

The DLL has two ranges of operation, slow and fast. The slow

range can be used for sample rates between 40MSPS and

100MSPS, while the default fast range can be used from

80MSPS to the maximum specified sample rate.

Jitter

In a sampled data system, clock jitter directly impacts the

achievable SNR performance. The theoretical relationship

between clock jitter (tJ) and SNR is shown in Equation 1 and is

illustrated in Figure 32.

This relationship shows the SNR that would be achieved if clock

jitter were the only non-ideal factor. In reality, achievable SNR is

limited by internal factors such as linearity, aperture jitter and

thermal noise. Internal aperture jitter is the uncertainty in the

sampling instant shown in Figure1A. The internal aperture jitter

combines with the input clock jitter in a root-sum-square fashion,

since they are not statistically correlated, and this determines

the total jitter in the system. The total jitter, combined with other

noise sources, then determines the achievable SNR.

Voltage Reference

A temperature compensated internal voltage reference provides

the reference charges used in the successive approximation

operations. The full-scale range of each A/D is proportional to the

reference voltage. The nominal value of the voltage reference is

1.25V.

Digital Outputs

Output data is available as a parallel bus in

LVDS-compatible(default) or CMOS modes. In either case, the data

is presented in either double data rate (DDR) or single data rate

(default) format. Figures 1A and 1B show the timing relationships

for LVDS and CMOS modes, respectively.

Additionally, the drive current for LVDS mode can be set to a

nominal 3mA(default) or a power-saving 2mA. The lower current

setting can be used in designs where the receiver is in close

physical proximity to the A/D. The applicability of this setting is

dependent upon the PCB layout, therefore the user should

experiment to determine if performance degradation is

observed. Note that a far-end termination resistor is required in

LVDS mode for correct operation.

The output mode can be controlled through the SPI port, by

writing to address 0x73, see “Serial Peripheral Interface” on

page 25.

An external resistor creates the bias for the LVDS drivers. A 10k

Ω,

1% resistor must be connected from the RLVDS pin to OVSS.

Over-Range Indicator

The over-range (OR) bit is asserted when the magnitude of the

analog input exceeds positive or negative fullscale of the ADC.

The output code does not wrap around during an over-range

condition. The OR bit is updated at the sample rate.

Power Dissipation

The power dissipated by the ISLA214P12 is primarily dependent

on the sample rate and the output modes: LVDS vs CMOS and

DDR vs SDR. There is a static bias in the analog supply, while the

remaining power dissipation is linearly related to the sample

rate. The output supply dissipation changes to a lesser degree in

LVDS mode, but is more strongly related to the clock frequency in

CMOS mode.

Nap/Sleep

Portions of the device may be shut down to save power during

times when operation of the A/D is not required. Two power saving

modes are available: Nap, and Sleep. Nap mode reduces power

dissipation to < 60mW while Sleep mode reduces power

dissipation to 9mW typically.

All digital outputs (Data, CLKOUT and OR) are placed in a high

impedance state during Nap or Sleep. The input clock should

remain running and at a fixed frequency during Nap or Sleep, and

CSB should be high. Recovery time from Nap mode will increase

if the clock is stopped, since the internal DLL can take up to

100µs to regain lock at 125MSPS.

By default after the device is powered on, the operational state is

controlled by the NAPSLP pin as shown in Table 2.

TABLE 1. CLKDIV PIN SETTINGS

CLKDIV PIN

DIVIDE RATIO

AVSS

Float

AVDD

SNR

20 log

πf

INtJ

--------------------

⎝⎠

⎛⎞

(EQ. 1)

FIGURE 32. SNR vs CLOCK JITTER

tj = 100ps

tj = 10ps

tj = 1ps

tj = 0.1ps

10 BITS

12 BITS

14 BITS

100

10M

100M

INPUT FREQUENCY (Hz)

TABLE 2. NAPSLP PIN SETTINGS

NAPSLP PIN

MODE

AVSS

Normal

Float

Sleep

AVDD

Nap

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