DM385 datasheet(165/281 Pages) TI

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DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

8.4

EDMA

The EDMA controller handles all data transfers between memories and the device slave peripherals on

the device. These data transfers include cache servicing, non-cacheable memory accesses, user-

programmed data transfers, and host accesses.

8.4.1

EDMA Channel Synchronization Events

The EDMA channel controller supports up to 64 channels which service peripherals and memory. Each

EDMA channel is mapped to a default EDMA synchronization event as shown in Table 8-2. In addition,

each EDMA channel can alternatively be mapped to one of the 31 multiplexed EDMA synchronization

events shown in Table 8-3. The EVT_MUX_x registers in the Control Module are used to select between

the default event and the multiplexed events for each channel.

For more detailed information on the EDMA module and how EDMA events are enabled, captured,

processed, linked, chained, cleared, and more, see the Enhanced Direct Memory Access Controller

chapter in the device-specific Technical Reference Manual.

Table 8-2. EDMA Default Synchronization Events

EVENT

DEFAULT

DEFAULT EVENT DESCRIPTION

NUMBER

EVENT NAME

0-1

–

Reserved

SDTXEVT1

SD1 Transmit

SDRXEVT1

SD1 Receive

4-7

–

Reserved

AXEVT0

McASP0 Transmit

AREVT0

McASP0 Receive

AXEVT1

McASP1 Transmit

AREVT1

McASP1 Receive

–

Reserved

–

Reserved

–

Reserved

–

Reserved

SPI0XEVT0

SPI0 Transmit 0

SPI0REVT0

SPI0 Receive 0

SPI0XEVT1

SPI0 Transmit 1

SPI0REVT1

SPI0 Receive 1

SPI0XEVT2

SPI0 Transmit 2

SPI0REVT2

SPI0 Receive 2

SPI0XEVT3

SPI0 Transmit 3

SPI0REVT3

SPI0 Receive 3

SDTXEVT0

SD0 Transmit

SDRXEVT0

SD0 Receive

UTXEVT0

UART0 Transmit

URXEVT0

UART0 Receive

UTXEVT1

UART1 Transmit

URXEVT1

UART1 Receive

UTXEVT2

UART2 Transmit

URXEVT2

UART2 Receive

32-35

–

Reserved

ISS_DMA_REQ1

ISS Event 1

ISS_DMA_REQ2

ISS Event 2

ISS_DMA_REQ3

ISS Event 3

Peripheral Information and Timings

165

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