DM385 datasheet(100/281 Pages) TI

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DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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Table 3-53. Video Input 1 (Digital) Terminal Functions (continued)

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

VIN[1]A_D[16]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

M11

R Port A data inputs.

VIN[1]A_D[17]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

L12

R Port A data inputs.

VIN[1]A_D[18]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

M10

R Port A data inputs.

VIN[1]A_D[19]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

R Port A data inputs.

VIN[1]A_D[20]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

R Port A data inputs.

VIN[1]A_D[21]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

R Port A data inputs.

VIN[1]A_D[22]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

R Port A data inputs.

VIN[1]A_D[23]

Video Input 1 Data inputs. For RGB capture, D[23:16] are I

R Port A data inputs.

VIN[1]A_DE

Video Input 1 Port A Data Enable input. Discrete data

valid signal for Port A YCbCr capture modes without

embedded syncs (BT.601 modes).

VIN[1]A_FLD

Video Input 1 Port A Field ID input. Discrete field

identification signal for Port A YCbCr capture modes

without embedded syncs (BT.601 modes).

VIN[1]A_HSYNC

Video Input 1 Port A Horizontal Sync input. Discrete

horizontal synchronization signal for Port A YCbCr

capture modes without embedded syncs (BT.601

modes).

VIN[1]A_VSYNC

Video Input 1 Port A Vertical Sync input. Discrete vertical

synchronization signal for Port A YCbCr capture modes

without embedded syncs (BT.601 modes).

VIN[1]B_CLK

Video Input 1 Port B Clock input. Input clock for 8-bit Port

AF2

B video capture. Input data is sampled on the CLK1

edge. This signal is not used in 16-bit and 24-bit capture

modes.

VIN[1]B_D[0]

Video Input Port B Data inputs. For 8-bit capture,

AG4