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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM385 датащи(PDF) 157 Page - Texas Instruments |
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DM385 датащи(HTML) 157 Page - Texas Instruments |
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157 / 281 page  DM385, DM388 www.ti.com SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 Table 7-24. Maximum SYSCLK Clock Frequencies (continued) MAX CLOCK FREQUENCY SYSCLK OPP100 (MHz) SYSCLK18 0.032768 SYSCLK19 192 SYSCLK20 192 SYSCLK21 192 SYSCLK22 RSV SYSCLK23 RSV 7.4.8 Module Clocks Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 7-25 lists the clock source options for each Module on this device, along with the maximum frequency that Module can accept. To ensure proper Module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table. Table 7-25. Maximum Module Clock Frequencies MAX FREQUENCY MODULE CLOCK SOURCE(S) OPP100 (MHz) PLL_ARM Cortex-A8 600 SYSCLK18 DDR0 PLL_DDR 400 DMM PLL_DDR/2 200 EDMA SYSCLK4 220 SERDES EMAC Switch (GMII) Fixed 125 PLL_VIDEO0 PLL_VIDEO0 EMAC Switch (RGMII) Fixed 250 SERDES SERDES EMAC Switch (RMII and MII) PLL_VIDEO0 Fixed 50 EMAC_RMREFCLK Pin Face Detect SYSCLK4 220 GPIO SYSCLK6 110 GPIO Debounce SYSCLK18 Fixed 0.032768 GPMC SYSCLK6 110 HDMI PLL_VIDEO2 186 HDMI CEC SYSCLK10 Fixed 48 SYSCLK20 SYSCLK21 HDMI I2S 50 AUD_CLK0/1/2 AUX Clock HDVICP2 SYSCLK3 266 HDVPSS PLL_HDVPSS 200 PLL_VIDEO2 HDVPSS VOUT1 186 HDMI PHY PLL_VIDEO1 HDVPSS VOUT0 165 PLL_VIDEO2 HDVPSS SD VENC PLL_VIDEO0 Fixed 54 PLL_VIDEO0 HDVPSS HD VENC PLL_VIDEO1 Fixed 148.5 HDMI I2C0/1/2/3 SYSCLK10 48 ISS PLL_ MEDIACTL 400 L3 Fast SYSCLK4 220 Copyright © 2013, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 157 Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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