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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM385 датащи(PDF) 143 Page - Texas Instruments |
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DM385 датащи(HTML) 143 Page - Texas Instruments |
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143 / 281 page  RESET STATE DEV_CLKIN/ AUX_CLKIN (A) POR RESET BTMODE[15:0] Other I/O Pins (C) Power Supplies Ramping Power Supplies Stable Clock Source Stable 2 3 5 Config 5 Hi-Z 7 RSTOUT_WD_OUT 9 BTMODE[11] (B) 1 Hi-Z DM385, DM388 www.ti.com SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 Figure 7-5 shows the Power-Up Timing. Figure 7-6 shows the Warm Reset (RESET) Timing. Max Reset Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not re-latched. A. Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of tw(RESET). B. RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset. C. For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also see , Terminal Functions for the IPU/IPD settings during reset. Figure 7-5. Power-Up Timing Copyright © 2013, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 143 Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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