AM1806 datasheet(71/245 Pages) TI

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OSCOUT

OSCIN

OSCVSS

Clock

Input

toPLL

AM1806

www.ti.com

SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

Figure 6-7. External 1.2V Clock Source

Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock

MIN

MAX

UNIT

fOSCIN

OSCIN frequency range

MHz

tc(OSCIN)

Cycle time, external clock driven on OSCIN

tw(OSCINH)

Pulse width high, external clock on OSCIN

0.4 tc(OSCIN)

tw(OSCINL)

Pulse width low, external clock on OSCIN

0.4 tc(OSCIN)

tt(OSCIN)

Transition time, OSCIN

0.25P or 10 (1)

tj(OSCIN)

Period jitter, OSCIN

0.02P

(1)

Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve

noise immunity on input signals.

6.6

Clock PLLs

The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides

clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the

mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows

the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.

The PLL controller provides the following:

•

Glitch-Free Transitions (on changing clock settings)

•

Domain Clocks Alignment

•

Clock Gating

•

PLL power down

The various clock outputs given by the controller are as follows:

•

Domain Clocks: SYSCLK [1:n]

•

Auxiliary Clock from reference clock source: AUXCLK

Various dividers that can be used are as follows:

•

Post-PLL Divider: POSTDIV

•

SYSCLK Divider: D1, ¼, Dn

Various other controls supported are as follows:

•

PLL Multiplier Control: PLLM

•

Software programmable PLL Bypass: PLLEN

Peripheral Information and Electrical Specifications

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