PUSB3F96

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 3 — 29 September 2014

4 of 15

NXP Semiconductors

PUSB3F96

ESD protection for ultra high-speed interfaces

differential mode

Fig 1.

Insertion loss; typical values

Fig 2.

Relative capacitance as a function of input

voltage; typical values

Sdd21 normalized to 100

;

differential pairs CH1/CH2 versus CH3/CH4

(1) PUSB3F96 on reference board

(2) Reference board without device under test (DUT)

Fig 3.

Crosstalk; typical values

Fig 4.

Differential Time Domain Reflectometer (TDR)

plot; typical values

aaa-009367

-6

-10

-2

2

(dB)

-14

f (MHz)

05

4

23

1

aaa-009368

0.4

0.8

1.2

a

0

a

C

line

C

line V

I

0 V

=



---------------------------------

=

aaa-009369

-40

-20

0

(dB)

-60

f (MHz)

t (ns)

40.0

42.0

41.5

40.5

41.0

aaa-009370

100

90

110

120

(Ω)

80

(1)

(2)