Ensuring a Valid

RESET Output

no longer sinks current—it becomes an open circuit.

Therefore, high-impedance CMOS logic inputs con-

nected to the RESET output can drift to undetermined

voltages. This presents no problem in most applica-

tions, since most

µP and other circuitry is inoperative

RESET output must be valid down to 0V, adding a pull-

down resistor to the RESET pin will cause any stray

leakage currents to flow to ground, holding RESET low

(Figure 2a). R1’s value is not critical; 100k

Ω is large

enough not to load RESET, and small enough to pull

RESET to ground.

A 100k

for the MAX822 if RESET is required to remain valid for

Interfacing to µPs with

Bidirectional Reset Pins

µPs with bidirectional reset pins (such as the Motorola

68HC11 series) can contend with the MAX821 reset

output. For example, if the MAX821 RESET output is

asserted high and the µP wants to pull it low, indetermi-

nate logic levels may result. To correct such cases,

connect a 4.7k

Ω resistor between the MAX821 RESET

output and the µP reset I/O (Figure 3). Buffer the reset

output to other system components.

___________________Chip Information

TRANSISTOR COUNT: 492

4-Pin µP Voltage Monitors with Pin-Selectable

Power-On Reset Timeout Delay

6

_______________________________________________________________________________________

4.7k

GND

RESET

MAX821

RESET

GND

µP

BUFFER

BUFFERED RESET

TO OTHER SYSTEM

COMPONENTS

Figure 3. Interfacing to µPs with Bidirectional Reset I/O

R1

GND

MAX821

RESET

R1

GND

MAX822

RESET

a)

b)