Baseband Signal Processor

18

MX829 PRELIMINARY INFORMATION

© 1998 MX

•COM Inc.

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Doc. # 20480160.004

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6.1 Programming the MX829

The MX829 should be programmed in the following manner:

1.

Perform a General Reset when first applying power to the MX829.

2.

Program the MX829 configuration while in powersave.

e.g.

UK/F, MIC, B/W, 1200/2400, DTMF0-3, DTMFHI, DTMFLO, TXIDLEM, RXDATAM, TXDATAM,

RX SYNC WORD PRIME, SYNT PRIME, SYNC PRIME, MOD1, MOD2, RX SYNC WORD and AUDIO

ATTENUATOR.

3.

Take the appropriate parts of the MX829 out of powersave by enabling:

AMP1, AMP2, MOD1, MOD2, AUDIO and (DTMFEN or MSKTX or MSKRX).

4.

In DTMF Tx mode, a DTMF tone will be generated for the duration that DTMFEN is set to “1”.

5.

In MSK Rx mode, wait for an interrupt ( IRQ = “0”) or poll the STATUS register. Remember that all status flags are

reset after reading the STATUS register.

A. If RXSYNCWORDF, SYNTF or SYNCF become set to “1”, the corresponding synchronization word has been

detected. This indicates the start of valid Rx data. The checksum calculation will be automatically reset. Note

that the timing of RXDATAF will be re-aligned by the generation of a SYNC, SYNT or RX SYNC WORD

interrupt.

B. When RXDATAF subsequently becomes set to “1”, read the Rx data from the RXDATA register. (Note that

RXDATAF will be set every 8 bits regardless of whether valid Rx data is being received or not. Sync and

checksum patterns should be considered for validating the data).

C. If RXSUMF becomes set to “1”, then all of the Rx data sent (starting after the synchronization word and

terminating with a checksum) will have been correctly received. Note that it is necessary to know in advance

what message length is expected, in order to determine at which point RXSUMF is valid (i.e. after the interrupt

for the second checksum data byte being received has occurred). The RXSUMF bit is invalid at all other times.

When RXSUMF becomes set to “1”, the last two bytes of Rx data received will represent the two-byte

checksum transmitted. The first checksum byte will already have been read from the RXDATA register, the last

byte is available to be read, as the RXDATAF bit will also have been set to “1”.

6.

In MSK Tx mode, wait for an interrupt ( IRQ = “0”) or poll the STATUS register. Remember that all status flags are

reset after reading the STATUS register.

A. Do not send Tx data until the TXDATAF bit has been set to “1”. When the TXDATAF bit is next set to “1”, write

the first byte of Tx data to the TXDATA register. If the transmit buffer is empty, this data will be transmitted

immediately, causing the TXDATAF bit to be set to “1” approximately one MSK bit-period after the TXDATA

register has been loaded with data. (Any TXIDLEF bit set upon entering MSK Tx mode should be ignored).

B. The next byte of Tx data should be written to the TXDATA register as soon as the TXDATAF bit has been set to

“1”. Once this has been done, the TXDATAF bit will again be set to “1” eight MSK bit-periods after the TXDATA

register was loaded with the second byte of data.

C. Subsequent bytes of Tx data should be written to the TXDATA register as soon as the TXDATAF bit has been

set to”1”. After the last byte of Tx data has been loaded, the TXDATAF bit will be set after both 8 and 16 MSK

bit-periods followed by the TXIDLEF bit which will be set approximately one MSK bit-period later, to indicate

that the final bit has been transmitted.

D. The TXDATAF bit will continue to be set every 8 MSK bit-periods, regardless of whether Tx data is written to

the TXDATA register or not, providing the transmitter is enabled (MSK Tx mode = MSKTX bit set to “1”). Note

that while the 2-byte checksum is being generated and transmitted, the TXDATAF bit will not be set for

approximately 24 MSK bit-periods.