CMX910 datasheet(43/61 Pages) CMLMICRO

43 / 61 page

AIS Baseband Processor

CMX910

D/910/6

DAC0 data register: 16-bit write only.

C-BUS Address $70

DAC1 data register: 16-bit write only.

C-BUS Address $71

DAC2 data register: 16-bit write only.

C-BUS Address $72

DAC3 data register: 16-bit write only.

C-BUS Address $73

DAC4 data register: 16-bit write only.

C-BUS Address $74

All bits cleared to 0 on reset.

Bit:

$70:

Reserved, set to 000000

DAC0 data (written by C-BUS, or from DAC RAM in ramp mode)

$71:

Reserved, set to 000000

DAC1 data

$72:

Reserved, set to 000000

DAC2 data

$73:

Reserved, set to 000000

DAC3 data

$74:

Reserved, set to 000000

DAC4 data

DAC_Control register: 8-bit write only.

C-BUS Address $75

All bits cleared to 0 on reset.

Bit:

DAC

RAM

Load

C-BUS

Ramp

Control

DAC0

Ramp

Mode

DAC4

DAC3

DAC2

DAC1

DAC0

DAC_Control register b7: DAC RAM Load

Setting b7 = 1 to this bit causes DAC0 to immediately enter DAC RAM load mode, causing the

internal DAC RAM address pointer to be reset to 0. The DAC RAM can then be loaded by

repeatedly writing data to the C-BUS DAC_RAM_Load register. While in DAC RAM load mode,

any attempt to write directly to the DAC0 data register will be ignored, as will any attempt to

initiate a ramp-up or ramp-down sequence (whether issued automatically by the CMX910 or from

the C-BUS). As soon as the µC has finished loading the DAC RAM, DAC_Control register b7 can

be taken low again.

DAC_Control register b6: C-BUS Ramp Control

If DAC0 is in ramp mode, the state of this register bit determines how the ramp-up and ramp-

down functions are controlled: b6 = 0 for automatic control by the CMX910, b6 = 1 for control via

the C-BUS commands DAC0_Rampup and DAC0_Rampdown.

DAC_Control register b5: DAC0 Ramp Mode

Setting DAC_Control b5 = 1 at the same time as DAC_Control b7 = 0 puts DAC0 into ramp mode.

The internal DAC RAM address pointer immediately gets reset to 0, an initial read of the DAC

RAM is performed and the resulting data is transferred to the DAC0 data register. The circuit then

responds to any subsequent ramp-up and ramp-down commands. While in ramp mode, any

attempt to write directly to the DAC0 data register will be ignored, as will any attempt to write to

the DAC RAM using the DAC_RAM_Load register.

Note: if both DAC_Control b7 = 0 and b5 = 0, the µC is able to write directly to the DAC0 data

ignored:

DAC0 data register can be written directly by µC

DAC0 in ramp mode, automatically controlled by the CMX910

DAC0 in ramp mode, controlled by the µC

DAC0 in DAC RAM load mode

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