CCFL Backlight and

LCD Contrast Controllers

______________________________________________________________________________________

13

Positive LCD Bias: MAX754

The voltage-regulation loop is comprised of resistors R3

and R4, the pulse-skip comparator, the internal DAC,

the on-time and off-time logic, and the external power

components. The comparator compares a fraction of

the output voltage to the voltage generated by an on-

chip 6-bit DAC. The part regulates by keeping the volt-

age at LFB equal to the DAC’s output voltage. Thus,

you can set the output to different voltages by varying

the DAC’s output.

Varying the DAC output voltage (digital control) adjusts

the external voltage from 50% to 100% of full scale. On

power-up or after a reset, the counter sets the DAC out-

put to mid scale. Each rising edge of LADJ (with LON

high) decrements the DAC output. When decremented

beyond zero scale, the counter rolls over and sets the

DAC to the maximum value. In this way, a single pulse

applied to LADJ decreases the DAC set point by one

step, and 63 pulses increase the set point by one step.

The MAX754’s DAC transfer function is shown in Figure 7.

The following equation relates the switching regulator’s

regulated output voltage to the DAC’s voltage:

Table 5 is the logic table for the LADJ and LON inputs,

which control the internal DAC and counter. As long as the

timing specifications for LADJ and LON are observed, any

sequence of operations can be implemented.

Negative LCD Bias: MAX753

The LCD bias generator of the MAX753 (Figure 8) gen-

erates its negative output by combining the switching

regulator of the MAX754 with a simple diode-capacitor

voltage inverter. To best understand the circuit, look at

the part in a steady-state condition. Assume, for

instance, that the output is being regulated to -30V, and

that the battery voltage is +10V. When Q3 turns on, two

things occur: current ramps up in the inductor, just like

with the boost converter; and the charge on C15 (trans-

ferred from the inductor on the previous cycle) is trans-

ferred to C6, boosting the negative output. At the end of

the cycle, the voltage on C15 is 30V + Vd, where Vd is

the forward voltage drop of Schottky diode D3, and 30V

is the magnitude of the output.

When the MOSFET turns off, the inductor’s energy is

transferred to capacitor C15, charging the capacitor to

this instance, diode D8 allows current to flow from the

right-hand side of the flying capacitor (C15) to ground.

When the MOSFET turns on, the left-hand side of

capacitor C15 is clamped to ground, forcing the right-

the output, forcing D3 to conduct, and transferring

charge from the flying capacitor C15 to the output

capacitor C6. This charge transfer happens quickly,

resulting in a voltage spike at the output due to the

product of the output capacitor’s equivalent series

resistance (ESR) and the current that flows from C15 to

C6. To limit this drop, resistor R19 has been placed in

series with D3. R19 limits the rate of current flow. At the

end of this cycle, the flying capacitor has been dis-

charged to 30V + Vd.

If BATT(MAX) (i.e., either the fully charged battery volt-

age, or the wall-cube voltage) is greater than

GND, as shown by the dashed lines in Figure 8.

Efficiency is lower with this method, so tie the cathode

of D8 to GND whenever possible.

The MAX753’s regulation loop is similar to that of the

MAX754. The MAX753, however, uses different power

components, and its feedback resistors are returned to

the reference (1.25V) rather than ground.

The MAX753’s PFM comparator compares a fraction of

the output voltage to the voltage generated by the on-

chip 6-bit DAC. The part regulates by keeping the volt-

age at LFB equal to the DAC’s output voltage. Thus,

you can set the LCD bias voltage to different voltages

by varying the DAC’s output.

VV

1

R3

R4

OUT

DAC

=+









01

635

645

655

2

DAC CODE

ZERO SCALE

MID SCALE

FULL SCALE

30 31 32

61 62 63

928

938

947

1230

1240

1250

Figure 7. MAX754 LCD DAC Transfer Function