be unable to regulate the current correctly. As the sup-

ply voltage drops further, the LED segment drive cur-

rent becomes effectively limited by the output drivers'

on-resistance, and the LED drive current drops. The

characteristics of each individual LED in a modern 7-

segment digit usually match well, so the result is that

the display intensity dims uniformly as supply voltage

drops out of regulation and beyond. The MAX6950/

MAX6951 operate down to 2V supply voltage (although

most displays are very dim at this voltage), providing

that the MAX6950/MAX6951 are powered up initially to

at least 2.7V to trigger the device's internal reset, and

also that the SPI interface is constrained to 5Mbps.

Computing Power Dissipation

The upper limit for power dissipation (PD) for the

MAX6950/MAX6951 is determined from the following

equation:

Where:

V+ = supply voltage

DUTY = duty cycle set by intensity register

N = number of segment driven (worst case is 8)

PD = power dissipation, in mW if currents are in mA

Dissipation example:

40mA, V+ = 3.6V

= 0.414W

+120°C/W), the maximum allowed ambient temperature

+120°C/W)

safely at a maximum package temperature of +85°C.

Power Supplies

The MAX6950/MAX6951 operate from a single +2.7V to

+5.5V power supply. Bypass the power supply to

ground with a 0.1µF capacitor as close to the pin as

possible. Add a 22µF capacitor if the MAX6950/

MAX6951 are not close to the board’s input bulk decou-

pling capacitor.

Connect the underside exposed pad to GND.

Board Layout

When designing a board, use the following guidelines:

with very short tracks.

routes directly to pin 8, and that this track is not

used as part of any other ground connection.

Figure 5 shows a good layout. The decoupling capaci-

tors C1 (ceramic) and C2 (bulk, if required) are located

track from both the IC's power ground connection and

the ground plane.

Serially Interfaced, +2.7V to +5.5V,

5- and 8-Digit LED Display Drivers

16

______________________________________________________________________________________

Table 17. Digit Register Mapping with

Blink Globally Disabled

SEGMENT’S

BIT SETTING

IN PLANE P1

SEGMENT’S

BIT SETTING

IN PLANE P0

SEGMENT

BEHAVIOR

X0

Segment off during both

halves of each blink

period

X1

Segment off during both

halves of each blink

period

Table 18. Digit Register Mapping with

Blink Globally Enabled

SEGMENT’S

BIT SETTING

IN PLANE P1

SEGMENT’S

BIT SETTING

IN PLANE P0

SEGMENT

BEHAVIOR

00

Segment off

01

Segment on only during

the 1st half of each blink

period

10

Segment on only during

the 2nd half of each blink

period

11

Segment on