MAX686EEE datasheet(4/16 Pages) MAXIM

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DAC-Controlled Boost/Inverter

LCD Bias Supply with Internal Switch

_______________________________________________________________________________________

ISET = VCC

0.4

0.6

SHDN = GND

ILX

LX Switch Current Limit

POL = GND, VFB = 1.3V, IDACOUT = 0mA

ISET = GND

VCC = VDD = 5V, ILX = 100mA

0.2

0.3

Ω

1.2

VLX = 28V

Rising or falling

µA

1.5

CONDITIONS

ILXLEAK

LX Leakage Current

RLX

LX On-Resistance

VCC = VDD = 3.3V, ILX = 100mA

1.6

µs

7.5

12.5

tON

Maximum LX On-Time

POL = GND, VFB > 1.2V

µs

0.7

1.3

tOFF

Minimum LX Off-Time

POL = VCC, VFB < 0.15V

2.8

4.2

POL = GND, VFB < 0.8V

3.8

6.2

POL = VCC, VFB > 0.4V

3.8

6.2

µA

ISHDN

Shutdown Current

µA

125

ICC + IDD

2.7

5.5

VCC, VDD

Supply Voltage (Note 1)

Supply Current

VLX

LX Voltage Range

2.10

2.65

VLOCK

VCC Undervoltage Lockout

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

ELECTRICAL CHARACTERISTICS

(VCC = VDD = VIN = +5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted.) (Note 4)

Note 1: The MAX686 requires a supply voltage at VCC = VDD between +2.7V and +5.5V; however, the voltage that supplies the

inductor can vary from +0.8V to +27.5V, depending on circuit operating conditions.

Note 2: The DAC output is set to its midpoint value at power-on.

Note 3: The DAC setting is guaranteed to remain valid as long as VCC is greater than the VCC DAC Reset Threshold.

Note 4: Specifications to -40°C are guaranteed by design, not production tested.

VCC = VDD = 2.7V to 5.5V, no load

1.22

1.28

VREF

REF Output Voltage

IREF = 0µA to 25µA, CREF = 0.1µF

REF Load Regulation

POL = GND

1.22

1.28

VFB

FB Set Point

POL = VCC

-15

±50

IFB

FB Input Bias Current

VPOK rising

1.05

1.20

VPOK

POK Threshold

±50

IPOK

POK Input Current

V LCDON = 0.4V, VPOK = 1.25V

ILCDON

LCDON Sink Current

Voltage applied to L1

0.8

VOUT

VIN

Input Voltage

-50µA < IDACOUT < 0µA

VREF -

VREF +

0.02

VFS

Full-Scale Output Voltage

0µA < IDACOUT < 20µA

VZS

Zero-Scale Output Voltage

Bits

Resolution

Mid-scale = VREF x 32/63

-3

MSA

Mid-Scale Accuracy

2.7V < VCC = VDD < 5.5V

0.7

VIL

Input Low Level

2.7V < VCC = VDD < 5.5V

2.4

VIH

Input High Level

µA

±1

IBIAS

Input Bias Current

REFERENCE AND FB INPUT

POWER OK COMPARATOR, LCDON OUTPUT

LOGIC INPUTS: POL, ISET, UP, DN, SHDN

DAC OUTPUT (Notes 2, 3)

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