Detailed Description

RESET/RESET Output

A microprocessor’s (µP’s) reset input starts the µP in a

known state. The MAX6826–MAX6831 µP supervisory

circuits assert a reset to prevent code-execution errors

during power-up, power-down, and brownout condi-

tions. Whenever a monitored voltage falls below the

reset threshold, the reset output asserts low for RESET

and high for RESET. Once all monitored voltages

exceed their reset thresholds, an internal timer keeps

the reset output asserted for the specified reset timeout

original state (Figure 3).

Manual Reset Input

Many µP-based products require manual-reset capabil-

ity, allowing the operator, a test technician, or external

logic circuitry to initiate a reset. A logic low on MR

asserts a reset. Reset remains asserted while MR is

low, and for the timeout period (140ms min) after it

returns high. MR has an internal 50k

Ω pullup resistor,

so it can be left open if not used. This input can be dri-

ven with CMOS logic levels or with open-drain/collector

Dual Ultra-Low-Voltage SOT23 µP Supervisors

with Manual Reset and Watchdog Timer

8

_______________________________________________________________________________________

MAX6829/MAX6830/MAX6831

WDI

OR

RESET

RESET

MR

RESET TIMEOUT

DELAY GENERATOR

1.26V

0.63V

WATCHDOG

TIMER

WATCHDOG

TRANSITION

DETECTOR

1V

1V

RESET

GND

RESET

Figure 3. Reset Timing Diagram