TSI721 datasheet(49/68 Pages) IDT

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3. Electrical Characteristics > AC Timing Specifications

Tsi721 Datasheet

May 5, 2014

Formal Status

This document is confidential and is subject to an NDA.

Integrated Device Technology

3.7.4.0.2

Level I Receiver Eye Diagram

For each baud rate at which the a LP-Serial receiver is specified to operate, the receiver meets the corresponding Bit Error

Ratio specification in Table 25 when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within

the unshaded portion of the Receiver Input Compliance Mask displayed in Figure 9. The eye pattern of the receiver test signal

is measured at the input pins of the receiving device with the device replaced with a 100 Ohm + 5% differential resistive load.

Figure 9: S-RIO Level I Receiver Input Mask

3.7.4.1

5 Gbps LP-Serial Links

This chapter describes the requirements for Level II RapidIO LP-Serial short and medium electrical interfaces of nominal baud

rates of 5.0. Gbps using NRZ coding (thus, 1 bit per symbol at the electrical level). A compliant device must meet all of the

requirements listed below. The electrical interface is based on a high speed low voltage logic with a nominal differential

impedance of 100 Ohm. Connections are point-to-point balanced differential pair and signaling is unidirectional.

Table 25: Level I Far-End (Rx) Template Intervals

Characteristic

Symbol

Far-End

Value

Units

Eye mask

R_X1

0.275

Eye mask

R_Y1

100

Eye mask

R_Y2

800

High probability jitter

R_HPJ

0.37

UIpp

Total Jitter (Does not include sinusoidal

jitter)

R_TJ

0.55

UIpp

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