_______________Detailed Description

Reset Function/Output

The reset output is typically connected to the reset

input of a microprocessor (µP). A µP’s reset input starts

or restarts the µP in a known state. The MAX6301–

MAX6304 µP supervisory circuits provide the reset

logic to prevent code-execution errors during power-

up, power-down, and brownout conditions (see

Typical

Operating Circuit).

For the MAX6301/MAX6303,

RESET changes from high

period, then goes high. When a reset is asserted due to

a watchdog timeout condition,

RESET stays low for the

reset timeout period. Anytime reset asserts, the watch-

dog timer clears. At the end of the reset timeout period,

RESET goes high and the watchdog timer is restarted

from zero. If the watchdog timeout period is exceeded

again, then

RESET goes low again. This cycle contin-

ues unless WDI receives a transition.

teed to be a logic low. For information about applica-

Ensuring a Valid

and

RESET remains low. When the reset timeout period

ends,

RESET goes high.

below 1V. For information about applications where

MAX6304).

The MAX6302/MAX6304 active-high RESET output is

the inverse of the MAX6301/MAX6303 active-low

Reset Threshold

These supervisors monitor the voltage on RESET IN.

The MAX6301–MAX6304 have an adjustable reset

voltage divider (Figure 1). Use the following formula to

age triggers a reset):

R2 can have very high values to minimize current con-

sumption. Set R2 to some conveniently high value (1M

Ω,

for example) and calculate R1 based on the desired

reset threshold voltage, using the following formula:

Watchdog Timer

The watchdog circuit monitors the µP’s activity. If the µP

(user selected), reset asserts. The internal watchdog

timer is cleared by reset, by a transition at WDI (which

can detect pulses as short as 30ns), or by a transition

at WDS. The watchdog timer remains cleared while

reset is asserted; as soon as reset is released, the timer

starts counting (Figure 2).

The MAX6301–MAX6304 feature two modes of watch-

dog timer operation: normal mode and extended mode.

In normal mode (WDS = GND), the watchdog timeout

period is determined by the value of the capacitor con-

nected between SWT and ground (see the section

Selecting the Reset and Watchdog Timeout Capacitor).

period is multiplied by 500. For example, in the extend-

ed mode, a 1µF capacitor gives a watchdog timeout

period of 22 minutes (see the graph Extended-Mode

Operating Characteristics).

In extended mode, the watchdog function can be dis-

abled by leaving WDI unconnected or by three-stating

the driver connected to WDI. In this mode, the watch-

dog input is internally driven low during the watchdog

R1 R2

V

V

1

RST

TH

=×

−







Ω

V

VR1 R2

R2

V

RST

TH

=

×+

() ()

0.1µF

MAX6301

MAX6302

MAX6303

MAX6304

RESET IN

R2

R1

R2

+5V, Low-Power µP Supervisory Circuits

with Adjustable Reset/Watchdog

6

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