| поискавой системы для электроныых деталей |
|
ISO7142CCDBQ датащи(PDF) 13 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ISO7142CCDBQ датащи(HTML) 13 Page - Texas Instruments |
|
13 / 26 page ![]() ISO7142CC www.ti.com SLLSEF1B – SEPTEMBER 2013 – REVISED AUGUST 2015 8.3 Feature Description 8.3.1 Insulation and Safety-Related Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DTI Distance through the insulation Minimum internal gap (internal clearance) 0.014 mm CI (1) Input capacitance VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 2 pF DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIOTM Maximum transient isolation voltage 4242 VPK VIORM Maximum working isolation voltage 566 VPK After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, 679 Partial discharge < 5 pC Method a, After environmental tests subgroup 1, VPR Input-to-output test voltage VPR = VIORM x 1.6, t = 10 s, 906 VPK Partial discharge < 5 pC Method b1, 100% production test, VPR = VIORM x 1.875, t = 1 s, 1061 Partial discharge < 5 pC L(I01) Minimum air gap (clearance) Shortest terminal to terminal distance through air 3.7 mm Minimum external tracking Shortest terminal to terminal distance across the L(I02) 3.7 mm (creepage) package surface Pollution degree 2 Tracking resistance (comparative CTI DIN EN 60112 (VDE 0303-11); IEC 60112 ≥400 V tracking index) VIO = 500 V, TA = 25 oC >1012 RIO (2) Isolation resistance, input to output VIO = 500 V, 100 oC ≤ T A ≤ 125 oC >1011 Ω VIO = 500 V, TS = 150 oC >109 CIO (2) Barrier capacitance, input to output VI = 0.4 sin (2πft), f = 1 MHz 2.4 pF UL 1577 Withstanding Isolation voltage VTEST = VISO= 2500 VRMS, 60 sec (qualification); VISO VTEST = 1.2 * VISO= 3000 VRMS, 1 sec (100% 2500 VRMS production) (1) Measured from input data pin to ground. (2) All pins on each side of the barrier tied together creating a two-terminal device. spacer NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. Table 1. IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS SPECIFICATION Material Group II Rated mains voltage ≤ 150 VRMS I–IV Installation classification / Overvoltage Category for Basic Insulation Rated mains voltage ≤ 300 VRMS I–III Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: ISO7142CC |
|
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |