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S1004 датащи(PDF) 32 Page - Seiko Instruments Inc |
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S1004 датащи(HTML) 32 Page - Seiko Instruments Inc |
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32 / 42 page ![]() BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN S-1004 Series Rev.2.1_00 Seiko Instruments Inc. 32 17. Release delay time (tRESET) vs. Power supply voltage (VDD) S-1004Cx10 Ta = +25°C, CD = 4.7 nF 8.0 6.0 10.0 2.0 4.0 11 15 VDD [V] 14 13 12 16 0.0 1 s tRESET VIH*1 SENSE pin voltage Output voltage VIL*2 VDD VSS VDD 90% *1. VIH = 10 V *2. VIL = 0.95 V Figure 36 Test Condition of Release Delay Time VDD VDD VSS OUT R 100 k Ω SENSE P.G. Oscilloscope CD CD VDD VDD VSS OUT SENSE P.G. Oscilloscope CD CD Figure 37 Test Circuit of Release Delay Time Figure 38 Test Circuit of Release Delay Time (Nch open-drain output product) (CMOS output product) Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. |
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