Quad, 10-Bit, Low-Power, 2-Wire, Serial

Voltage-Output DAC

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9

a STOP (P) condition. Each word transmitted over the

bus is 8 bits long and is always followed by an

acknowledge clock pulse.

The MAX5841 SDA and SCL drivers are open-drain

outputs, requiring a pullup resistor to generate, a logic

high voltage (see Typical Operating Circuit). Series

the input stages of the MAX5841 from high-voltage

spikes on the bus lines, and minimize crosstalk and

undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. The data on SDA must remain stable during the

high period of the SCL clock pulse. Changes in SDA

while SCL is high are control signals (see START and

STOP Conditions). Both SDA and SCL idle high when

START and STOP Conditions

When the serial interface is inactive, SDA and SCL idle

high. A master device initiates communication by issu-

ing a START condition. A START condition is a high-to-

low transition on SDA with SCL high. A STOP condition

is a low-to-high transition on SDA, while SCL is high

(Figure 2). A START condition from the master signals

the beginning of a transmission to the MAX5841. The

master terminates transmission by issuing a not

acknowledge followed by a STOP condition (see

Acknowledge Bit (ACK)). The STOP condition frees the

instead of a STOP condition, the bus remains active.

When a STOP condition or incorrect address is detect-

ed, the MAX5841 internally disconnects SCL from the

serial interface until the next START condition, minimiz-

ing digital noise and feedthrough.

Early STOP Conditions

The MAX5841 recognizes a STOP condition at any

point during transmission except if a STOP condition

occurs in the same high pulse as a START condition

least one clock pulse must separate any START and

STOP conditions.

Repeated START Conditions

change of data direction on the bus. Such a change

occurs when a command word is required to initiate a

want to relinquish control of the bus. The MAX5841 ser-

ial interface supports continuous write operations with

POWER-DOWN

COMMAND BITS

PD1

PD0

MODE/FUNCTION

00

Power-up device. DAC output

restored to previous value.

01

Power-down mode 0. Power down

device with output floating.

10

Power-down mode 1. Power down

device with output terminated with

1k

Ω to GND.

11

Power-down mode 2. Power down

device with output terminated with

100k

Ω to GND.

Table 1. Power-Down Command Bits

SCL

SDA

STOP

CONDITION

START

CONDITION

REPEATED START CONDITION

START CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram