Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

Device

ACK By

Device

Frame 3 Two-Wire Slave Address Byte

Frame 4 Data Byte 1 Read Register

Start By

Master

ACK By

Device

NACK By

Master

(2)

From

Device

1

9

1

9

1

9

1

9

SDA

SCL

0

0

1

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

¼

¼

SDA

(Continued)

SCL

(Continued)

1

0

0

1

1

0

0

(1)

1

0

0

(1)

D7

D6

D5

D4

D3

D2

D1

D0

Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

Device

ACK By

Device

1

9

1

Frame 3 Data Byte 1

ACK By

Device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

1

0

0

(1)

P7

P6

P5

P4

P3

P2

P1

P0

¼

¼

Stop By

Master

TMP451-Q1

SLOS877 – OCTOBER 2014

www.ti.com

Programming (continued)

(1) Slave address 1001100 shown.

Figure 15. Two-Wire Timing Diagram for Write Word Format

(1) Slave address 1001100 shown.

(2) Master should leave SDA high to terminate a single-byte read operation.

Figure 16. Two-Wire Timing Diagram for Single-Byte Read Format

7.5.1.3 Serial Bus Address

To communicate with the TMP451-Q1 device, the master must first address slave devices using a slave address

byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing

a read or write operation. The TMP451-Q1 device has a device address of 4Ch (1001 100b). Additional factory-

programmed device addresses are available upon request.

14

Submit Documentation Feedback

Copyright © 2014, Texas Instruments Incorporated

Product Folder Links: TMP451-Q1