 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
S1721 датащи(PDF) 21 Page - Seiko Instruments Inc |
|
|
|||||||||||||||||||||||||||||
S1721 датащи(HTML) 21 Page - Seiko Instruments Inc |
|
|
21 / 42 page  SUPER-SMALL PACKAGE 2-CIRCUIT HIGH RIPPLE-REJECTION LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.2.0_00 S-1721 Series Seiko Instruments Inc. 21 Operation 1. Basic operation Figure 23 shows the block diagram of S-1721 Series. The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-divided by feedback resistors Rs and Rf. It supplies the gate voltage necessary to maintain the constant output voltage which is not influenced by the input voltage and temperature change, to the output transistor. *1 *1. Parasitic diode VSS Current supply − + Vfb Vref VIN VOUT Rf Rs Error amplifier Reference voltage circuit Figure 23 2. Output transistor In the S-1721 Series, a low on-resistance P-channel MOS FET is used as the output transistor. Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to inverse current flowing from the VOUT pin through a parasitic diode to the VIN pin. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
