ICS831742I Data Sheet

4:2 DIFFERENTIAL CLOCK/DATA MULTIPLEXER

ICS831742AGI JULY 10, 2012

11

©2012 Integrated Device Technology, Inc.

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other

requirements. Figures 2A to 2E show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the

vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 2A, the input termination

applies for IDT open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 2A. CLK/nCLK Input Driven by an IDT Open

Emitter HiPerClockS LVHSTL Driver

Figure 2C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 2E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 2B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 2D. CLK/nCLK Input Driven by a

3.3V LVDS Driver

R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

R3

125

Ω

R4

125

Ω

R1

84

Ω

R2

84

Ω

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

3.3V

LVPECL

Differential

Input

HCSL

*R333

*R4

33

CLK

nCLK

2.5V

3.3V

Zo = 50

Ω

Zo = 50

Ω

Differential

Input

R1

50

R2

50

*Optional – R3 and R4 can be 0

Ω

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

R1

50

Ω

R2

50

Ω

R2

50

Ω

3.3V

R1

100

Ω

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω