ICS8543BGI REVISION E NOVEMBER 15, 2012

3

©2012 Integrated Device Technology, Inc.

ICS8543I Data Sheet

LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

Inputs

Outputs

OE

CLK_EN

CLK_SEL

Selected Source

Q0:Q3

nQ0:nQ3

0

X

X

Hi-Z

Hi-Z

1

0

0

CLK/nCLK

Disabled; Low

Disabled; High

1

0

1

PCLK/nPCLK

Disabled; Low

Disabled; High

1

1

0

CLK/nCLK

Enabled

Enabled

1

1

1

PCLK/nPCLK

Enabled

Enabled

Inputs

Outputs

Input to Output Mode

Polarity

CLK or PCLK

nCLK or nPCLK

Q[0:3]

nQ[0:3]

0

1

LOW

HIGH

Differential to Differential

Non-Inverting

1

0

HIGH

LOW

Differential to Differential

Non-Inverting

0

Biased; NOTE 1

LOW

HIGH

Single-Ended to Differential

Non-Inverting

1

Biased; NOTE 1

HIGH

LOW

Single-Ended to Differential

Non-Inverting

Biased; NOTE 1

0

HIGH

LOW

Single-Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single-Ended to Differential

Inverting

Enabled

Disabled

CLK_EN

CLK, PCLK

nCLK, nPCLK

Q0:Q3

nQ0:nQ3