ICS8312 datasheet(8/18 Pages) IDT

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ICS8312

LOW SKEW, 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

ICS8312AY REV. D JULY 3, 2008

Table 5C. AC Characteristics, VDD = VDDO = 1.8V ± 0.2V, TA = 0°C to 85°C

All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.

Using the same type of input on each device, the output is measured at VDDO/2.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C to 85°C

All parameters measured at fMAX unless noted otherwise.

NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.

Using the same type of input on each device, the output is measured at VDDO/2.

NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

fMAX

Output Frequency

200

MHz

tpLH

Propagation Delay, Low to High; NOTE 1

≤ 200MHz

1.6

3.3

4.8

tjit

Buffer Additive Phase Jitter, RMS; refer to

Additive Phase Jitter Section

100MHz, Integration Range:

12kHz – 20MHz

0.172

tsk(o)

Output Skew; NOTE 2, 5

140

tsk(pp)

Part-to-Part Skew; NOTE 3, 5

2.3

tR / tF

Output Rise/Fall Time; NOTE 5

20% to 80%

200

800

odc

Output Duty Cycle

≤ 100MHz